Bernard Brezzo

Publication Activity (10 Years)

Years Active: 1996-2015
Publications (10 Years): 2

Top Topics

Linear Equations

Top Venues

Int. J. Parallel Program.

Publications

Bharat Sukhwani, Mathew Thoennes, Hong Min, Parijat Dube, Bernard Brezzo, Sameh W. Asaad, Donna Dillenberger
A Hardware/Software Approach for Database Query Acceleration with FPGAs. Int. J. Parallel Program. 43 (6) (2015)
Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (10) (2015)
Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Bernard Brezzo, Sameh W. Asaad, Donna Dillenberger
Database Analytics: A Reconfigurable-Computing Approach. IEEE Micro 34 (1) (2014)
Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC (2014)
Bharat Sukhwani, Mathew Thoennes, Hong Min, Parijat Dube, Bernard Brezzo, Sameh W. Asaad, Donna Dillenberger
Large Payload Streaming Database Sort and Projection on FPGAs. SBAC-PAD (2013)
Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad
Efficient in-system RTL verification and debugging using FPGAs (abstract only). FPGA (2012)
Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. FPGA (2012)
Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Balakrishna Iyer, Bernard Brezzo, Donna Dillenberger, Sameh W. Asaad
Database analytics acceleration using FPGAs. PACT (2012)
Bharat Sukhwani, Bülent Abali, Bernard Brezzo, Sameh W. Asaad
High-Throughput, Lossless Data Compresion on FPGAs. FCCM (2011)
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC (2011)
Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin
Single-chip 4×500-MBd CMOS transceiver. IEEE J. Solid State Circuits 31 (12) (1996)