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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.

Jae-sun SeoBernard BrezzoYong LiuBenjamin D. ParkerSteven K. EsserRobert K. MontoyeBipin RajendranJosé A. TiernoLeland ChangDharmendra S. ModhaDaniel J. Friedman
Published in: CICC (2011)
Keyphrases
  • learning process
  • high speed
  • spiking neurons
  • analog vlsi
  • spiking neural networks
  • learning algorithm
  • low cost
  • learning mechanism
  • circuit design
  • biologically plausible
  • cmos technology