Daniel J. Friedman

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 15

Top Topics

Quantum Computing

Gigabit Ethernet

Top Venues

IEEE J. Solid State Circuits

VLSI Technology and Circuits

Publications

Raphael Robertazzi, David J. Frank, Kevin Tien, John Timmerwilke, Peilin Song, Daniel J. Friedman
Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays. VTS (2024)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58 (4) (2023)
David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
Low power cryogenic RF ASICs for quantum computing. CICC (2023)
Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
Cryogenic CMOS: design considerations for future quantum computing systems. CICC (2023)
David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. ISSCC (2022)
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits (2022)
Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. IEEE J. Solid State Circuits 57 (11) (2022)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits (2022)
Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. DATE (2022)
Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55 (6) (2020)
Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS (2018)
Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. ISSCC (2017)
Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Mark A. Ferriss, Duixian Liu, Daniel J. Friedman, Alberto Valdes-Garcia
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. IEEE J. Solid State Circuits 52 (12) (2017)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51 (8) (2016)
Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. ISSCC (2016)
Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC (2015)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50 (8) (2015)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC (2015)
Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Daniel J. Friedman
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test 31 (6) (2014)
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits 49 (4) (2014)
Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC (2014)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC (2014)
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48 (4) (2013)
Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. CICC (2013)
Glenn E. R. Cowan, Mounir Meghelli, Daniel J. Friedman
A linearized voltage-controlled oscillator for dual-path phase-locked loops. ISCAS (2013)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48 (6) (2013)
Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2013)
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC (2013)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48 (5) (2013)
Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC (2013)
Jean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC (2012)
Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. ISSCC (2012)
Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. IEEE J. Solid State Circuits 47 (12) (2012)
Yong Liu, Wing K. Luk, Daniel J. Friedman
A compact low-power 3D I/O in 45nm CMOS. ISSCC (2012)
John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47 (12) (2012)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits 47 (4) (2012)
Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC (2012)
John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC (2012)
John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. IEEE J. Solid State Circuits 47 (4) (2012)
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC (2012)
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC (2011)
Daniel J. Friedman, R. Gibson Parrish II
The population health record: concepts, definition, design, and implementation. J. Am. Medical Informatics Assoc. 17 (4) (2010)
Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. IEEE J. Solid State Circuits 44 (4) (2009)
Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. IEEE J. Solid State Circuits 44 (12) (2009)
Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC (2009)
John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. ISSCC (2009)
Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. ISSCC (2009)
Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. ISSCC (2009)
Kyu-hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. ISSCC (2008)
Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. CICC (2008)
Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC (2008)
José A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. IEEE J. Solid State Circuits 43 (1) (2008)
Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. IEEE J. Solid State Circuits 42 (4) (2007)
Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. ISSCC (2007)
Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. IEEE J. Solid State Circuits 42 (8) (2007)
Matt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman
A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver. ISSCC (2007)
Yong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. ISSCC (2007)
James F. Buckwalter, Mounir Meghelli, Daniel J. Friedman, Ali Hajimiri
Phase and amplitude pre-emphasis techniques for low-power serial links. IEEE J. Solid State Circuits 41 (6) (2006)
John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41 (12) (2006)
Baharak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget
An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback. CICC (2006)
Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC (2006)
Woogeun Rhee, Benjamin D. Parker, Daniel J. Friedman
A semi-digital delay-locked loop using an analog-based finite state machine. IEEE Trans. Circuits Syst. II Express Briefs (11) (2004)
Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC (2003)
Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. CICC (2003)
Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. IEEE J. Solid State Circuits 38 (12) (2003)
Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer
SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. 47 (2-3) (2003)
James J. Clark, Daniel J. Friedman
VLSI sensori-motor systems. ICRA (1991)