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A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.

John F. BulzacchelliMounir MeghelliSergey V. RylovWoogeun RheeAlexander V. RylyakovHerschel A. AinspanBenjamin D. ParkerMichael P. BeakesAichin ChungTroy J. BeukemaPetar K. PepeljugoskiLei ShanYoung Hoon KwarkSudhir M. GowdaDaniel J. Friedman
Published in: IEEE J. Solid State Circuits (2006)
Keyphrases
  • cmos technology
  • low power
  • spl times
  • high speed
  • power consumption
  • low voltage
  • parallel processing
  • low cost
  • power dissipation
  • silicon on insulator
  • design methodology
  • random access memory