Mounir Meghelli

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 29

Top Topics

Gate Dielectrics

Optical Networks

Top Venues

IEEE J. Solid State Circuits

VLSI Technology and Circuits

Publications

Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC (2024)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58 (4) (2023)
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits (2022)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits (2022)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". IEEE J. Solid State Circuits 55 (4) (2020)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. IEEE J. Solid State Circuits 55 (1) (2020)
Benjamin G. Lee, Nicolas Dupuis, Fuad E. Doany, Laurent Schares, Nicolas Boyer, Nathalie Normand, Herschel A. Ainspan, Christian W. Baks, Jonathan E. Proesel, Isabel De Sousa, Mounir Meghelli, Marc A. Taubenblatt
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. OFC (2019)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. ISSCC (2019)
Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). OFC (2019)
Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53 (4) (2018)
Mounir Meghelli, Hyeon-Min Bae, Frank O'Mahony
Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. ISSCC (2018)
Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53 (4) (2018)
Benjamin G. Lee, Nicolas Dupuis, Jason Orcutt, Javier Ayala, Karen Nummy, Herschel A. Ainspan, Jonathan E. Proesel, Christian W. Baks, Douglas M. Gill, Mounir Meghelli, William M. J. Green
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. OFC (2018)
Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC (2018)
Bo Zhang, Frederic Gianesello, Simone Erba, Mounir Meghelli, Azita Emami, Takayuki Shibasaki
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. ISSCC (2018)
Rahel Strässle, Sebastian Gerke, Thomas Brunschwiler, Yuksel Temiz, Jonas R. M. Weiss, Arvind Sridhar, Stephan Paredes, Emanuel Loertscher, Neil Ebejer, Bruno Michel, H.-M. Lee, C. Alvarado, Ismael Faro, T. van Kessel, Mounir Meghelli, Marc A. Taubenblatt, Sufi Zafar, Frank Libsch, Keiji Matsumoto
Internet of the Body and Cognitive Hypervisor. CHASE (2017)
Tim Piessens, Seung-Tak Ryu, Chih-Ming Hung, Alyosha C. Molnar, Mounir Meghelli
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 52 (12) (2017)
Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52 (12) (2017)
Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC (2017)
Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. ISSCC (2017)
Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. ISSCC (2016)
Jason S. Orcutt, Douglas M. Gill, Jonathan E. Proesel, J. Ellis-Monaghan, Folkert Horst, Tymon Barwicz, Chi Xiong, Frederick G. Anderson, Ankur Agrawal, Yves Martin, Christian W. Baks, Marwan Khater, Jessie C. Rosenberg, W. D. Sacher, Jens Hofrichter, Edward Kiewra, Andreas D. Stricker, Frank Libsch, Bert Jan Offrein, Mounir Meghelli, Natalie B. Feilchenfeld, Wilfried Haensch, William M. J. Green
Monolithic silicon photonics at 25 Gb/s. OFC (2016)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51 (8) (2016)
Anand Ramaswamy, J. E. Roth, Erik J. Norberg, R. S. Guzzon, Jae-Hyuk Shin, J. T. Imamura, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish, B. G. Lee, Renato Rimolo-Donadio, Christian W. Baks, Alexander V. Rylyakov, Jonathan E. Proesel, Mounir Meghelli, Clint L. Schow
A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. OFC (2015)
Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli
22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. ISSCC (2015)
Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. IEEE J. Solid State Circuits 50 (12) (2015)
B. G. Lee, Renato Rimolo-Donadio, Alexander V. Rylyakov, Jonathan E. Proesel, John F. Bulzacchelli, Christian W. Baks, Mounir Meghelli, Clint L. Schow, Anand Ramaswamy, J. E. Roth, Jae-Hyuk Shin, B. Koch, Daniel K. Sparacin, Gregory A. Fish
A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. OFC (2015)
Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, B. Lee, John F. Bulzacchelli, Abhijeet Ardey, Clint Schow, Mounir Meghelli
A 25 Gb/s burst-mode receiver for low latency photonic switch networks. OFC (2015)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC (2015)
Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 49 (11) (2014)
Glenn E. R. Cowan, Mounir Meghelli, Daniel J. Friedman
A linearized voltage-controlled oscillator for dual-path phase-locked loops. ISCAS (2013)
Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47 (8) (2012)
Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology. CICC (2011)
Mounir Meghelli, Robert Shimon
Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08). IEEE J. Solid State Circuits 43 (10) (2008)
James F. Buckwalter, Mounir Meghelli, Daniel J. Friedman, Ali Hajimiri
Phase and amplitude pre-emphasis techniques for low-power serial links. IEEE J. Solid State Circuits 41 (6) (2006)
John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41 (12) (2006)
Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC (2006)
Mounir Meghelli
A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology. IEEE J. Solid State Circuits 40 (10) (2005)
Behnam Analui, Alexander V. Rylyakov, Sergey V. Rylov, Mounir Meghelli, Ali Hajimiri
A 10-Gb/s two-dimensional eye-opening monitor in 0.13-/spl mu/m standard CMOS. IEEE J. Solid State Circuits 40 (12) (2005)
Mounir Meghelli
132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology. IEEE J. Solid State Circuits 39 (12) (2004)
Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. CICC (2003)
Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. IEEE J. Solid State Circuits 38 (12) (2003)
Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer
SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. 47 (2-3) (2003)
Mounir Meghelli, Alexander V. Rylyakov, Lei Shan
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. IEEE J. Solid State Circuits 37 (12) (2002)
Greg G. Freeman, Mounir Meghelli, Young Kwark, Steven Zier, Alexander V. Rylyakov, Michael Sorna, Todd Tanji, Oswin M. Schreiber, Keith Walter, Jae-Sung Rieh, Basanth Jagannathan, Alvin J. Joseph, Seshadri Subbanna
SiGe technology. IEEE J. Solid State Circuits 37 (9) (2002)
Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE 88 (10) (2000)
Mounir Meghelli, Benjamin D. Parker, Herschel A. Ainspan, Mehmet Soyuer
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems. IEEE J. Solid State Circuits 35 (12) (2000)
Agnieszka Konczykowska, Mounir Meghelli
Very high speed integrated circuits for optical communication. ICECS (1998)
Philippe André, Jean-Louis Benchimol, Patrick Desrousseaux, Anne-Marie Duchenois, Jean Godin, Agnieszka Konczykowska, Mounir Meghelli, Muriel Riet, André Scavennec
InP DHBT technology and design methodology for high-bit-rate optical communications circuits. IEEE J. Solid State Circuits 33 (9) (1998)
Mounir Meghelli, Michel Bouché, Agnieszka Konczykowska
High power and high speed InP DHBT driver IC's for laser modulation. IEEE J. Solid State Circuits 33 (9) (1998)