A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Timothy O. DicksonYong LiuAnkur AgrawalJohn F. BulzacchelliHerschel A. AinspanZeynep Toprak DenizBenjamin D. ParkerMounir MeghelliDaniel J. FriedmanPublished in: CICC (2015)
Keyphrases
- silicon on insulator
- high speed
- cmos technology
- nm technology
- user interface
- random access memory
- parallel processing
- ibm power processor
- parallel implementation
- power consumption
- low power
- user friendly
- low cost
- video sequences
- bit parallel
- gigabit ethernet
- destination node
- delay insensitive
- asynchronous communication
- circuit design
- computer architecture
- parallel computing