Timothy O. Dickson

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 11

Top Topics

Delay Insensitive

Top Venues

IEEE J. Solid State Circuits

VLSI Technology and Circuits

Publications

Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC (2024)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58 (4) (2023)
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits (2022)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits (2022)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". IEEE J. Solid State Circuits 55 (4) (2020)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. IEEE J. Solid State Circuits 55 (1) (2020)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. ISSCC (2019)
Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). OFC (2019)
Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53 (4) (2018)
Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. ISSCC (2017)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51 (8) (2016)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50 (8) (2015)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC (2015)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC (2014)
Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. ISSCC (2012)
Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. IEEE J. Solid State Circuits 47 (12) (2012)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits 47 (4) (2012)
Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. IEEE J. Solid State Circuits 44 (4) (2009)
Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. IEEE J. Solid State Circuits 44 (12) (2009)
John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. ISSCC (2009)
Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. ISSCC (2009)
Sorin P. Voinigescu, Ricardo Andres Aroca, Timothy O. Dickson, Sean T. Nicolson, Theodoros Chalvatzis, Pascal Chevalier, Patrice Garcia, Christophe Gamier, Bernard Sautreuil
Towards a sub-2.5V, 100-Gb/s Serial Transceiver. CICC (2007)
Timothy O. Dickson, Sorin P. Voinigescu
Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS. IEEE J. Solid State Circuits 42 (10) (2007)
Timothy O. Dickson, Kenneth H. K. Yau, Theodoros Chalvatzis, Alain M. Mangan, Ekaterina Laskin, Rudy Beerkens, Paul Westergaard, Mihai Tazlauanu, Ming-Ta Yang, Sorin P. Voinigescu
The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks. IEEE J. Solid State Circuits 41 (8) (2006)
Kenneth K. O, Kihong Kim, Brian A. Floyd, Jesal L. Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, Eunyoung Seok, Joe E. Brewer, Li Gao, Aravind Sugavanam, Jau-Jr Lin, Y. Su, Changhua Cao, M.-H. Hwang, Yanping Ding, Zhenbiao Li, S.-H. Hwang, H. Wu, Swaminathan Sankaran, N. Zhang
Silicon Integrated Circuits Incorporating Antennas. CICC (2006)
Timothy O. Dickson, Rudy Beerkens, Sorin P. Voinigescu
A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic. IEEE J. Solid State Circuits 40 (4) (2005)
Kenneth K. O, Kihong Kim, Brian A. Floyd, Jesal L. Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, Eunyoung Seok, Li Gao, Aravind Sugavanam, Jau-Jr Lin, S. Yu, Changhua Cao, M.-H. Hwang, Y.-R. Ding, S.-H. Hwang, Hsin-Ta Wu, N. Zhang, Joe E. Brewer
The feasibility of on-chip interconnection using antennas. ICCAD (2005)
Timothy O. Dickson, Ekaterina Laskin, Imran Khalid, Rudy Beerkens, Jingqiong Xie, Boris Karajica, Sorin P. Voinigescu
An 80-Gb/s 2/sup 31/-1 pseudorandom binary sequence generator in SiGe BiCMOS technology. IEEE J. Solid State Circuits 40 (12) (2005)
Sorin P. Voinigescu, Timothy O. Dickson, Theodoros Chalvatzis, Altan Hazneci, Ekaterina Laskin, Rudy Beerkens, Imran Khalid, Edward S. Rogers Sr.
Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes. CICC (2005)
Paul Westergaard, Timothy O. Dickson, Sorin P. Voinigescu
A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis. CICC (2004)
Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, Kenneth K. O
Wireless interconnects for clock distribution. Timing Issues in the Specification and Synthesis of Digital Systems (2002)