A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
Timothy O. DicksonYong LiuAnkur AgrawalJohn F. BulzacchelliHerschel A. AinspanZeynep Toprak DenizBenjamin D. ParkerMichael P. BeakesMounir MeghelliDaniel J. FriedmanPublished in: IEEE J. Solid State Circuits (2016)