Herschel A. Ainspan

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 15

Top Topics

Optical Networks

Cmos Technology

Top Venues

IEEE J. Solid State Circuits

Publications

Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC (2024)
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits (2022)
Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55 (6) (2020)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". IEEE J. Solid State Circuits 55 (4) (2020)
Nicolas Dupuis, Jonathan E. Proesel, Nicolas Boyer, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Elaine Cyr, Benjamin G. Lee
An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability. OFC (2020)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. IEEE J. Solid State Circuits 55 (1) (2020)
Jonathan E. Proesel, Nicolas Dupuis, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee
A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS. VLSI Circuits (2020)
Benjamin G. Lee, Nicolas Dupuis, Fuad E. Doany, Laurent Schares, Nicolas Boyer, Nathalie Normand, Herschel A. Ainspan, Christian W. Baks, Jonathan E. Proesel, Isabel De Sousa, Mounir Meghelli, Marc A. Taubenblatt
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. OFC (2019)
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. ISSCC (2019)
Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). OFC (2019)
Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53 (4) (2018)
Benjamin G. Lee, Nicolas Dupuis, Jason Orcutt, Javier Ayala, Karen Nummy, Herschel A. Ainspan, Jonathan E. Proesel, Christian W. Baks, Douglas M. Gill, Mounir Meghelli, William M. J. Green
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. OFC (2018)
Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. ISSCC (2017)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51 (8) (2016)
Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. ISSCC (2016)
Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC (2015)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50 (8) (2015)
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC (2015)
Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. VLSIC (2015)
Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits 49 (4) (2014)
Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC (2014)
Franco Stellari, Peilin Song, Herschel A. Ainspan
Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements. VTS (2014)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC (2014)
John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47 (12) (2012)
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits 47 (4) (2012)
John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC (2012)
Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC (2009)
John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. ISSCC (2009)
Woogeun Rhee, Keith A. Jenkins, John C. Liobe, Herschel A. Ainspan
Experimental Analysis of Substrate Noise Effect on PLL Performance. IEEE Trans. Circuits Syst. II Express Briefs (7) (2008)
Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC (2008)
Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. IEEE J. Solid State Circuits 42 (8) (2007)
John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41 (12) (2006)
Baharak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget
An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback. CICC (2006)
Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC (2006)
Troy J. Beukema, Michael Sorna, Karl Selander, Steven J. Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. IEEE J. Solid State Circuits 40 (12) (2005)
Scott K. Reynolds, Brian A. Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. Ainspan
A direct-conversion receiver IC for WCDMA mobile systems. IEEE J. Solid State Circuits 38 (9) (2003)
Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC (2003)
Scott K. Reynolds, Brian A. Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. Ainspan
A direct-conversion receiver integrated circuit for WCDMA mobile systems. IBM J. Res. Dev. 47 (2-3) (2003)
Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer
SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. 47 (2-3) (2003)
Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE 88 (10) (2000)
Mounir Meghelli, Benjamin D. Parker, Herschel A. Ainspan, Mehmet Soyuer
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems. IEEE J. Solid State Circuits 35 (12) (2000)
Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer
A 5.2 GHz 3.3 V I/Q SiGe RF transceiver. CICC (1999)
Jungwook Yang, Joongho Choi, Daniel M. Kuchta, Kevin G. Stawiasz, Petar K. Pepeljugoski, Herschel A. Ainspan
A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology. IEEE J. Solid State Circuits 33 (12) (1998)
Joachim N. Burghartz, Daniel C. Edelstein, Mehmet Soyuer, Herschel A. Ainspan, Keith A. Jenkins
RF circuit design aspects of spiral inductors on silicon. IEEE J. Solid State Circuits 33 (12) (1998)
Mehmet Soyuer, Joachim N. Burghartz, Herschel A. Ainspan, Keith A. Jenkins, Peter Xiao, Arvin R. Shahani, Margaret S. Dolan, David L. Harame
An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator. IEEE J. Solid State Circuits 32 (9) (1997)
Mehmet Soyuer, Keith A. Jenkins, Joachim N. Burghartz, Herschel A. Ainspan, Frank J. Canora, Slaila Ponnapalli, John F. Ewen, William E. Pence
A 2.4-GHz silicon bipolar oscillator with integrated resonator. IEEE J. Solid State Circuits 31 (2) (1996)
Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin
Single-chip 4×500-MBd CMOS transceiver. IEEE J. Solid State Circuits 31 (12) (1996)
Daniel M. Kuchta, Herschel A. Ainspan, Frank J. Canora, Richard P. Schneider Jr.
Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier. IBM J. Res. Dev. 39 (1-2) (1995)
John F. Ewen, Mehmet Soyuer, Albert X. Widmer, Kevin R. Wrenner, Benjamin D. Parker, Herschel A. Ainspan
CMOS circuits for Gb/s serial data communication. IBM J. Res. Dev. 39 (1-2) (1995)
Mehmet Soyuer, Herschel A. Ainspan, John F. Ewen
A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery. ISCAS (1995)