A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery.

Mehmet Soyuer Herschel A. Ainspan John F. Ewen

Published in: ISCAS (1995)

Keyphrases

high speed
phase difference
feedback loop
low cost
low power
analog vlsi
database
low frequency
neural network
image processing
power consumption
learning phase
image recovery
preprocessing phase
multiresolution
vlsi circuits