A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
Timothy O. DicksonYong LiuSergey V. RylovAnkur AgrawalSeongwon KimPing-Hsuan HsiehJohn F. BulzacchelliMark A. FerrissHerschel A. AinspanAlexander V. RylyakovBenjamin D. ParkerMichael P. BeakesChristian W. BaksLei ShanYoung Hoon KwarkJosé A. TiernoDaniel J. FriedmanPublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- silicon on insulator
- ibm power processor
- cmos technology
- spl times
- decision feedback
- error resilience
- low power
- error propagation
- power consumption
- power management
- instruction set
- high speed
- input output
- low voltage
- parallel processing
- power dissipation
- scalable video coding
- low cost
- channel coding
- real time
- imaging systems
- floating point
- video quality
- file system