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Lei Shan
ORCID
Publication Activity (10 Years)
Years Active: 2002-2020
Publications (10 Years): 5
Top Topics
Kernel Independent Component Analysis
Spl Times
Negative Matrix Factorization
Cmos Technology
Top Venues
NCCET
CICC
ICSPCC
ISPA/IUCC
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Publications
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Lin Liang
,
Lei Shan
,
Fei Liu
,
Maolin Li
,
Ben Niu
,
Guanghua Xu
Impulse Feature Extraction of Bearing Faults Based on Convolutive Nonnegative Matrix Factorization.
IEEE Access
8 (2020)
Lei Shan
,
Canqun Yang
,
Weixia Xu
,
Minxuan Zhang
Heterogeneous acceleration for CNN training with many integrated core.
ICSPCC
(2017)
Naiyang Guan
,
Lei Shan
,
Canqun Yang
,
Weixia Xu
,
Minxuan Zhang
Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks.
ISPA/IUCC
(2017)
Lei Shan
,
He Wang
,
Weixia Xu
,
Canqun Yang
,
Minxuan Zhang
Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture.
NCCET
(2016)
Lei Shan
,
Minxuan Zhang
,
Lin Deng
,
Guohui Gong
A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network.
NCCET
(2016)
Timothy O. Dickson
,
Yong Liu
,
Sergey V. Rylov
,
Ankur Agrawal
,
Seongwon Kim
,
Ping-Hsuan Hsieh
,
John F. Bulzacchelli
,
Mark A. Ferriss
,
Herschel A. Ainspan
,
Alexander V. Rylyakov
,
Benjamin D. Parker
,
Michael P. Beakes
,
Christian W. Baks
,
Lei Shan
,
Young Hoon Kwark
,
José A. Tierno
,
Daniel J. Friedman
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits
50 (8) (2015)
W. Wei
,
Quan Xu
,
L. Wang
,
X. H. Hei
,
P. Shen
,
W. Shi
,
Lei Shan
GI/Geom/1 queue based on communication model for mesh networks.
Int. J. Commun. Syst.
27 (11) (2014)
Timothy O. Dickson
,
Yong Liu
,
Sergey V. Rylov
,
Ankur Agrawal
,
Seongwon Kim
,
Ping-Hsuan Hsieh
,
John F. Bulzacchelli
,
Mark A. Ferriss
,
Herschel A. Ainspan
,
Alexander V. Rylyakov
,
Benjamin D. Parker
,
Christian W. Baks
,
Lei Shan
,
Young Hoon Kwark
,
José A. Tierno
,
Daniel J. Friedman
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
CICC
(2014)
John F. Bulzacchelli
,
Mounir Meghelli
,
Sergey V. Rylov
,
Woogeun Rhee
,
Alexander V. Rylyakov
,
Herschel A. Ainspan
,
Benjamin D. Parker
,
Michael P. Beakes
,
Aichin Chung
,
Troy J. Beukema
,
Petar K. Pepeljugoski
,
Lei Shan
,
Young Hoon Kwark
,
Sudhir M. Gowda
,
Daniel J. Friedman
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.
IEEE J. Solid State Circuits
41 (12) (2006)
Daniel J. Friedman
,
Mounir Meghelli
,
Benjamin D. Parker
,
Jungwook Yang
,
Herschel A. Ainspan
,
Alexander V. Rylyakov
,
Young Hoon Kwark
,
Mark B. Ritter
,
Lei Shan
,
Steven J. Zier
,
Michael Sorna
,
Mehmet Soyuer
SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev.
47 (2-3) (2003)
Mounir Meghelli
,
Alexander V. Rylyakov
,
Lei Shan
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems.
IEEE J. Solid State Circuits
37 (12) (2002)