A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.
Woogeun RheeHerschel A. AinspanSergey V. RylovAlexander V. RylyakovMichael P. BeakesDaniel J. FriedmanSudhir M. GowdaMehmet SoyuerPublished in: CICC (2003)
Keyphrases
- high speed
- data sets
- high quality
- data sources
- data collection
- data points
- power consumption
- data acquisition
- data analysis
- synthetic data
- database
- data processing
- missing data
- high dimensional data
- data structure
- training data
- computer systems
- low cost
- knowledge discovery
- spatial data
- data distribution
- neural network
- data quality
- delay insensitive