Pier Andrea Francese

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 47

Top Topics

Functional Verification

Top Venues

IEEE J. Solid State Circuits

Publications

Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Serdar A. Yonar, Matthias Braendli, Andrea Ruffino, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC (2024)
Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Matthias Braendli, Marcel A. Kossel, Andrea Ruffino, Thomas Morf, Pier Andrea Francese, Gain Kim
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links. ISCAS (2024)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58 (4) (2023)
Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ISSCC (2023)
Sandro Widmer, Marcel A. Kossel, Giovanni Cherubini, Stanislaw Wozniak, Pier Andrea Francese, Ana Stanojevic, Matthias Brändli, Klaus Frick, Angeliki Pantazi
Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits (2022)
Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, Geethan Karunaratne, Matthias Brändli, Feng Liu, Abhairaj Singh, Silvia M. Müller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Fee Li Lie, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou
PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. IEEE J. Solid State Circuits 57 (4) (2022)
Mridula Prathapan, Peter Mueller, David Heim, Maria Vittoria Oropallo, Matthias Braendli, Pier Andrea Francese, Marcel A. Kossel, Andrea Ruffino, Cezar B. Zota, Eunjung Cha, Thomas Morf
A system design approach toward integrated cryogenic quantum control systems. CoRR (2022)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits (2022)
Mridula Prathapan, Peter Mueller, Christian Menolfi, Matthias Brändli, Marcel A. Kossel, Pier Andrea Francese, David Heim, Maria Vittoria Oropallo, Andrea Ruffino, Cezar B. Zota, Thomas Morf
A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control. ESSCIRC (2022)
Manuel Le Gallo, Riduan Khaddam-Aljameh, Milos Stanisavljevic, Athanasios Vasilopoulos, Benedikt Kersting, Martino Dazzi, Geethan Karunaratne, Matthias Braendli, Abhairaj Singh, Silvia M. Mueller, Julian Büchel, Xavier Timoneda Comas, Vinay Joshi, Urs Egger, Angelo Garofalo, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Timothy Philip, Victor Chan, Mary Claire Silvestre, Ishtiaq Ahsan, Nicole Saulnier, Vijay Narayanan, Pier Andrea Francese, Evangelos Eleftheriou, Abu Sebastian
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. CoRR (2022)
Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf, Cezar B. Zota
Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. ESSDERC (2021)
Marcel A. Kossel, Vishal Khatri, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Serdar A. Yonar, Mridula Prathapan, Eric J. Lukes, Raymond A. Richetta, Carrie Cox
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS. ISSCC (2021)
Riduan Khaddam-Aljameh, Pier Andrea Francese, Luca Benini, Evangelos Eleftheriou
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf, Cezar B. Zota
Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. ESSCIRC (2021)
Martino Dazzi, Abu Sebastian, Thomas P. Parnell, Pier Andrea Francese, Luca Benini, Evangelos Eleftheriou
Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification. IEEE Trans. Computers 70 (6) (2021)
Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, Geethan Karunaratne, Matthias Braendli, F. Liu, A. Singh, S. M. Müller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, S. Choi, Injo Ok, F. L. Lie, Nicole Saulnier, V. Chan, I. Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing. VLSI Circuits (2021)
Yang You, Glen A. Wiedemeier, Chad Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, Venkat Nammi, Jeffrey Okyere, Nathan Blanchard, Akil Sutton, Ze Zhang, David Friend, Diego Barba, Tyler Bohlke, Michael Spear, Vikram Raj, James Crugnale, Daniel Dreps, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf
A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS. VLSI Circuits (2020)
Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55 (1) (2020)
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC (2019)
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC (2019)
Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC (2019)
Martino Dazzi, Abu Sebastian, Pier Andrea Francese, Thomas P. Parnell, Luca Benini, Evangelos Eleftheriou
5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory. CoRR (2019)
Evangelos Eleftheriou, Manuel Le Gallo, S. R. Nandakumar, Christophe Piveteau, Irem Boybat, Vinay Joshi, Riduan Khaddam-Aljameh, Martino Dazzi, Iason Giannopoulos, Geethan Karunaratne, Benedikt Kersting, Milos Stanisavljevic, Vara Prasad Jonnalagadda, Nikolas Ioannou, Kornilios Kourtis, Pier Andrea Francese, Abu Sebastian
Deep learning acceleration based on in-memory computing. IBM J. Res. Dev. 63 (6) (2019)
Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53 (4) (2018)
Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53 (11) (2018)
Thomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits (2018)
Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese, Matthias Braendli, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. VLSI Circuits (2018)
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl, Yusuf Leblebici
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS (2018)
Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
30dB SNDR at nyquist in 14nm CMOS FinFET. ISSCC (2018)
Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits (2018)
Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC (2018)
Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Alessandro Cevrero, Marcel A. Kossel, Lukas Kull, Danny Luu, Ilter Özkaya, Thomas Toifl
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. ISSCC (2018)
Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53 (12) (2018)
Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits 53 (3) (2018)
Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52 (12) (2017)
Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC (2017)
Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC (2017)
Marcel A. Kossel, Christian Menolfi, Pier Andrea Francese, Lukas Kull, Thomas Morf, Thomas Toifl, Matthias Braendli, Alessandro Cevrero, Danny Luu, Ilter Özkaya, Hazar Yueksel
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. ESSCIRC (2017)
Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ESSCIRC (2017)
Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits 51 (3) (2016)
Phillip Stanley-Marbell, Pier Andrea Francese, Martin Rinard
Encoder logic for reducing serial I/O power in sensors and sensor hubs. Hot Chips Symposium (2016)
Thomas Toifl, Matthias Braendli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Ilter Özkaya, Hazar Yueksel
Design considerations for 50G+ backplane links. ESSCIRC (2016)
Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ISSCC (2016)
Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. ESSCIRC (2016)
Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, U. Bapst, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC (2015)
Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC (2015)
Toke Meyer Andersen, Florian Krismer, Johann Walter Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Pier Andrea Francese
20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. ISSCC (2015)
Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ISSCC (2015)
Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 49 (11) (2014)
Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. ESSCIRC (2014)
Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese
at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. ISSCC (2014)
Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC (2014)
Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
in 32 nm SOI CMOS. A-SSCC (2014)
Pier Andrea Francese, Thomas Toifl, Peter Buchmann, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. IEEE J. Solid State Circuits 49 (11) (2014)
Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC (2014)
Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Lukas Kull, Thomas Morf
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. ESSCIRC (2014)
Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. IEEE J. Solid State Circuits 48 (12) (2013)
Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC (2013)
Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC (2013)
Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits 48 (12) (2013)
Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC (2013)
Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. IEEE J. Solid State Circuits 47 (4) (2012)
Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Peter Buchmann, Pier Andrea Francese, Thomas Morf
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC (2012)
Robert C. Taft, Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, Alan MacKenzie, Tobias Hoehn, Philipp Schmitz, Heinz Werker, Andrew Glenny
A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency. IEEE J. Solid State Circuits 44 (12) (2009)
Robert C. Taft, Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, Alan MacKenzie, Tobias Hoehn, Philipp Schmitz, Heinz Werker, Andrew Glenny
A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency. ISSCC (2009)
Pier Andrea Francese, Pascal Ferrat, Qiuting Huang
A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering. IEEE J. Solid State Circuits 39 (12) (2004)