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A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET.

Alessandro CevreroIlter ÖzkayaPier Andrea FranceseMatthias BrändliChristian MenolfiThomas MorfMarcel A. KosselLukas KullDanny LuuMartino DazziThomas Toifl
Published in: ISSCC (2019)
Keyphrases
  • high speed
  • circuit design
  • learning algorithm
  • low cost
  • power consumption
  • low power
  • silicon on insulator