Matthias Brändli

ORCID

Publication Activity (10 Years)

Years Active: 2018-2023
Publications (10 Years): 11

Top Venues

IEEE J. Solid State Circuits

ISSCC

VLSI Technology and Circuits

VLSI Circuits

University of Zurich (PHD)

Education History

University of Zurich

PHD

Publications

Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58 (4) (2023)
Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ISSCC (2023)
Sandro Widmer, Marcel A. Kossel, Giovanni Cherubini, Stanislaw Wozniak, Pier Andrea Francese, Ana Stanojevic, Matthias Brändli, Klaus Frick, Angeliki Pantazi
Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits (2022)
Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, Geethan Karunaratne, Matthias Brändli, Feng Liu, Abhairaj Singh, Silvia M. Müller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Fee Li Lie, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou
PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. IEEE J. Solid State Circuits 57 (4) (2022)
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits (2022)
Mridula Prathapan, Peter Mueller, Christian Menolfi, Matthias Brändli, Marcel A. Kossel, Pier Andrea Francese, David Heim, Maria Vittoria Oropallo, Andrea Ruffino, Cezar B. Zota, Thomas Morf
A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control. ESSCIRC (2022)
Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC (2019)
Thomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits (2018)
Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits (2018)
Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53 (12) (2018)

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Publication Activity (10 Years)

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Matthias Brändli