Silvia M. Müller

Publication Activity (10 Years)

Years Active: 1988-2022
Publications (10 Years): 4

Top Topics

Software Design

Energy Efficiency

Ibm Power Processor

Top Venues

IBM J. Res. Dev.

IEEE J. Solid State Circuits

Publications

Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, Geethan Karunaratne, Matthias Brändli, Feng Liu, Abhairaj Singh, Silvia M. Müller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Fee Li Lie, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou
PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. IEEE J. Solid State Circuits 57 (4) (2022)
Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA (2021)
Robert F. Enenkel, Silvia M. Müller, Christopher K. Anand
Novel hardware & software design for mathematical and AI acceleration. CASCON (2020)
Anthony Saporito, Martin Recktenwald, Christian Jacobi, Gerrit Koch, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Craig R. Walters, Jang-Soo Lee, Cédric Lichtenau, Ulrich Mayer, Eduard Herkel, Stefan Payer, Silvia M. Müller, Vesselina K. Papazova, Ekaterina M. Ambroladze, Timothy C. Bronson
Design of the IBM z15 microprocessor. IBM J. Res. Dev. 64 (5/6) (2020)
Steven R. Carlough, Adam Collura, Silvia M. Müller, Michael Kroener
The IBM zEnterprise-196 Decimal Floating-Point Accelerator. IEEE Symposium on Computer Arithmetic (2011)
Maarten Boersma, Michael Kroener, Christophe Layer, Petra Leber, Silvia M. Müller, Kerstin Schelm
The POWER7 Binary Floating-Point Unit. IEEE Symposium on Computer Arithmetic (2011)
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51 (5) (2007)
Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough
IBM POWER6 accelerators: VMX and DFU. IBM J. Res. Dev. 51 (6) (2007)
Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. IEEE J. Solid State Circuits 41 (4) (2006)
Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. IEEE Symposium on Computer Arithmetic (2005)
Roger A. Golliver, Silvia M. Müller, Stuart F. Oberman, Martin S. Schmookler, Debjit Das Sarma, Andrew Beaumont-Smith
Pain versus Gain in the Hardware Design of FPUs and Supercomputers. IEEE Symposium on Computer Arithmetic (2005)
Guy Even, Silvia M. Müller, Peter-Michael Seidel
A dual precision IEEE floating-point multiplier. Integr. 29 (2) (2000)
Daniel Kröning, Wolfgang J. Paul, Silvia M. Müller
Proving the Correctness of Pipelined Micro-Architectures. MBMV (2000)
Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis
Parallel Computer Architecture. Euro-Par (2000)
Silvia M. Müller, Holger W. Leister, Peter Dell, Nikolaus Gerteis, Daniel Kroening
The Impact of Hardware Scheduling Mechanismus on the Performance and Cost of Processor Designs. ARCS (1999)
Silvia M. Müller
A Hardware Scheduler for Controlling Variable Latency Functional Units. Applied Informatics (1999)
Silvia M. Müller
On the Scheduling of Variable Latency Functional Units. SPAA (1999)
Silvia M. Müller, Wolfgang J. Paul
On the Correctness of Hardware Scheduling Mechanisms for Out-of-Order Execution. J. Circuits Syst. Comput. 8 (2) (1998)
Silvia M. Müller, Uzi Vishkin
Conflict-Free Access to Multiple Single-Ported Register Files. IPPS (1997)
Silvia M. Müller, Wolfgang J. Paul
Making the Original Scoreboard Mechanism Deadlock Free. ISTCS (1996)
Silvia M. Müller, Benedict Gomes
Efficient mapping of randomly sparse neural networks on parallel vector supercomputers. SPDP (1994)
Silvia M. Müller, Dieter Scheerer
A method to parallelize tridiagonal solvers. Parallel Comput. 17 (2-3) (1991)
Silvia M. Müller, Wolfgang J. Paul
Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers. IFIP Congress (1989)
P. Bergmann, Jörg Keller, Thomas Malter, Silvia M. Müller, Wolfgang J. Paul, Thorsten Pöschel, O. Schlüter, Lothar Thiele
Implementierung eines informationstheoretischen Ansatzes zur Bilderkennung. Innovative Informations-Infrastrukturen (1988)