Richard J. Eickemeyer

Publication Activity (10 Years)

Years Active: 1987-2021
Publications (10 Years): 1

Top Topics

Battery Powered

Energy Efficiency

Ibm Power Processor

Top Venues

IBM J. Res. Dev.

Publications

Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA (2021)
R. Raghavan, Richard J. Eickemeyer, Aaron Sawdey, John Griswell, D. Parikh, S. Ramani, D. M. Daly, N. Ni, B. Rogers, Alex E. Mericas, L. Maurice, K. Vu
IBM POWER8 performance and energy modeling. IBM J. Res. Dev. 59 (1) (2015)
Bülent Abali, Richard J. Eickemeyer, Hubertus Franke, Chung-Sheng Li, Marc Taubenblatt
Disaggregated and optically interconnected memory: when will it be cost effective? CoRR (2015)
Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler
IBM POWER8 processor core microarchitecture. IBM J. Res. Dev. 59 (1) (2015)
Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer
Abstraction and microarchitecture scaling in early-stage power modeling. HPCA (2011)
Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. IEEE J. Solid State Circuits 43 (4) (2008)
Harry M. Mathis, Alex E. Mericas, John D. McCalpin, Richard J. Eickemeyer, Steven R. Kunkel
Characterization of simultaneous multithreading (SMT) efficiency in POWER5. IBM J. Res. Dev. 49 (4-5) (2005)
Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner
POWER5 system microarchitecture. IBM J. Res. Dev. 49 (4-5) (2005)
Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA (2005)
John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel
A multithreaded PowerPC processor for commercial servers. IBM J. Res. Dev. 44 (6) (2000)
Steven R. Kunkel, Richard J. Eickemeyer, Mikko H. Lipasti, Timothy J. Mullins, Brian O'Krafka, Harold Rosenberg, Steven P. Vanderwiel, Philip L. Vitale, Larry D. Whitley
A performance methodology for commercial servers. IBM J. Res. Dev. 44 (6) (2000)
Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Beng-Hong Lim, Mark S. Squillante, Ching-Farn Eric Wu
Evaluation of Multithreaded Processors and Thread-Switch Policies. ISHPC (1997)
Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu
Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. ISCA (1996)
Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer
SCISM: A scalable compound instruction set machine. IBM J. Res. Dev. 38 (1) (1994)
Richard J. Eickemeyer, Stamatis Vassiliadis
A load-instruction unit for pipelined processors. IBM J. Res. Dev. 37 (4) (1993)
Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer
On the attributes of the SCISM organization. SIGARCH Comput. Archit. News 20 (4) (1992)
Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis
Interlock collapsing ALU for increased instruction-level parallelism. MICRO (1992)
Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis
Instruction-level parallelism from execution interlock collapsing. SIGARCH Comput. Archit. News 20 (4) (1992)
Richard J. Eickemeyer, Janak H. Patel
Performance Evaluation of On-Chip Register and Cache Organizations. ISCA (1988)
Richard J. Eickemeyer, Janak H. Patel
Performance Evaluation of Multiple Register Sets. ISCA (1987)