A load-instruction unit for pipelined processors.
Richard J. EickemeyerStamatis VassiliadisPublished in: IBM J. Res. Dev. (1993)
Keyphrases
- instruction set
- parallel architecture
- parallel processing
- instruction set architecture
- parallel algorithm
- processing units
- memory hierarchy
- load balance
- multimedia
- load balancing
- parallel computing
- floating point
- data flow
- neural network
- level parallelism
- cooperative learning
- multiprocessor systems
- computer assisted language learning
- computer assisted instruction
- parallel computers
- computing systems
- computer software
- load forecasting
- high end
- response time
- parallel computation
- computer architecture