Jens Leenstra

Publication Activity (10 Years)

Years Active: 1989-2015
Publications (10 Years): 2

Top Topics

Column Oriented

Advanced Features

Computational Intelligence

Ibm Power Processor

Top Venues

IBM J. Res. Dev.

Proc. VLDB Endow.

Publications

Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, J. Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block
Advanced features in IBM POWER8 systems. IBM J. Res. Dev. 59 (1) (2015)
Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler
IBM POWER8 processor core microarchitecture. IBM J. Res. Dev. 59 (1) (2015)
Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
POWER8 design methodology innovations for improving productivity and reducing power. CICC (2014)
Vijayshankar Raman, Gopi K. Attaluri, Ronald Barber, Naresh Chainani, David Kalmuk, Vincent KulandaiSamy, Jens Leenstra, Sam Lightstone, Shaorong Liu, Guy M. Lohman, Tim Malkemus, René Müller, Ippokratis Pandis, Berni Schiefer, David Sharpe, Richard Sidle, Adam J. Storm, Liping Zhang
DB2 with BLU Acceleration: So Much More than Just a Column Store. Proc. VLDB Endow. 6 (11) (2013)
Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46 (1) (2011)
Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding
Scan chain clustering for test power reduction. DAC (2008)
Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
Scan Test Planning for Power Reduction. DAC (2007)
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51 (5) (2007)
Joachim Fenkes, Tobias Gemmeke, Jens Leenstra
Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. J. Low Power Electron. 3 (1) (2007)
Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough
IBM POWER6 accelerators: VMX and DFU. IBM J. Res. Dev. 51 (6) (2007)
Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. ITC (2006)
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, Fellow, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41 (1) (2006)
Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller
The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum (2006)
Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller
The vector fixed point unit of the synergistic processor element of the cell architecture processor. ESSCIRC (2005)
Jens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. IEEE J. Solid State Circuits 36 (11) (2001)
Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC (2001)
David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44 (6) (2000)
Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. DAC (1997)
Jens Leenstra, Lambert Spaanenburg
Hierarchical Test Program Development for Scan Testable Circuits. ITC (1991)
Jens Leenstra, Lambert Spaanenburg
Hierarchical test assembly for macro based VLSI design. ITC (1990)
Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg
Issues in the test of artificial neural networks. ICCD (1989)
Jens Leenstra, Lambert Spaanenburg
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. ITC (1989)
Gerhard Roos, Jens Leenstra, Thomas Schwederski, Lambert Spaanenburg, Bernd Höfflinger
On structured gate forest VLSI design. Microprocessing and Microprogramming 27 (1-5) (1989)