DATE Designers' Forum

Keyphrases

Publications

2006

Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello
Software-friendly HW/SW co-simulation: an industrial case study. DATE Designers' Forum (2006)
Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek
Energy-efficient FPGA interconnect design. DATE Designers' Forum (2006)
Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Rosenstiel
Flexible specification and application of rule-based transformations in an automotive design flow. DATE Designers' Forum (2006)
Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano
GALS networks on chip: a new solution for asynchronous delay-insensitive links. DATE Designers' Forum (2006)
Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum (2006)
Vassilis Papaefstathiou, Ioannis Papaefstathiou
A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. DATE Designers' Forum (2006)
Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo
A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum (2006)
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti
Synthesis of system verilog assertions. DATE Designers' Forum (2006)
Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sanchez-Elez, Nader Bagherzadeh, Fredy Rivera
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). DATE Designers' Forum (2006)
Sergio Saponara, Pierangelo Terreni
Mixed-signal design of a digital input power amplifier for automotive audio applications. DATE Designers' Forum (2006)
Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud
Industrially proving the SPIRIT consortium specifications for design chain integration. DATE Designers' Forum (2006)
Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Architectures for efficient face authentication in embedded systems. DATE Designers' Forum (2006)
Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla
Modeling and simulation of mobile gateways interacting with wireless sensor networks. DATE Designers' Forum (2006)
Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum (2006)
Dmitry Akselrod, Asaf Ashkenazi, Yossi Amon
Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs. DATE Designers' Forum (2006)
Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis
Networks on chips for high-end consumer-electronics TV system architectures. DATE Designers' Forum (2006)
Götz Kappen, Tobias G. Noll
Application specific instruction processor based implementation of a GNSS receiver on an FPGA. DATE Designers' Forum (2006)
Giuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari
A mixed-signal verification kit for verification of analogue-digital circuits. DATE Designers' Forum (2006)
Luciano Bononi, Nicola Concer
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. DATE Designers' Forum (2006)
Ali Habibi, Haja Moinudeen, Sofiène Tahar
Generating finite state machines from SystemC. DATE Designers' Forum (2006)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum (2006)
Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller
The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum (2006)
Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum (2006)
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
STAX: statistical crosstalk target set compaction. DATE Designers' Forum (2006)
Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi, Luigi Sportiello
). DATE Designers' Forum (2006)
Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE Designers' Forum (2006)
Pierluigi Daglio
A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories. DATE Designers' Forum (2006)
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives. DATE Designers' Forum (2006)
Fabiano Costa Carvalho, Carlos Eduardo Pereira, Elias Teodoro Silva Jr., Edison Pignaton de Freitas
A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN. DATE Designers' Forum (2006)
Luca Serafini, F. Carrai, T. Ramacciotti, V. Zolesi
Multi-sensor configurable platform for automotive applications. DATE Designers' Forum (2006)
John Dielissen, Andries Hekstra, Vincent Berg
Low cost LDPC decoder for DVB-S2. DATE Designers' Forum (2006)
Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo
Design and test of fixed-point multimedia co-processor for mobile applications. DATE Designers' Forum (2006)
Michele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò
3dID: a low-power, low-cost hand motion capture device. DATE Designers' Forum (2006)
G. Zarri, Federico Colucci, F. Dupuis, Riccardo Mariani, Mario Pasquariello, G. Risaliti, C. Tibaldi
On the verification of automotive protocols. DATE Designers' Forum (2006)
Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum (2006)
Federico Baronti, Paolo D'Abramo, Martin Knaipp, Rainer Minixhofer, Roberto Roncella, Roberto Saletti, Martin Schrems, Riccardo Serventi, Verena Vescoli
FlexRay transceiver in a 0.35 µm CMOS high-voltage technology. DATE Designers' Forum (2006)
Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. DATE Designers' Forum (2006)
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006 DATE Designers' Forum (2006)
Kai Richter, Rolf Ernst
How OEMs and suppliers can face the network integration challenges. DATE Designers' Forum (2006)
Sutjipto Arifin, Peter Y. K. Cheung
A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. DATE Designers' Forum (2006)
Andreas Raabe, Stefan Hochgürtel, Joachim K. Anlauf, Gabriel Zachmann
Space-efficient FPGA-accelerated collision detection for virtual prototyping. DATE Designers' Forum (2006)
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum (2006)
Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera
Interconnection framework for high-throughput, flexible LDPC decoders. DATE Designers' Forum (2006)
Daniele Lo Iacono, J. Zory, Ettore Messina, Nicolo Piazzese, G. Saia, A. Bettinelli
ASIP architecture for multi-standard wireless terminals. DATE Designers' Forum (2006)
Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
A new approach to compress the configuration information of programmable devices. DATE Designers' Forum (2006)
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum (2006)