H. Peter Hofstee

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 47

Top Topics

Top Venues

J. Signal Process. Syst.

Publications

Yongding Tian, Zaid Al-Ars, Maksim Kitsak, H. Peter Hofstee
Vanishing Variance Problem in Fully Decentralized Neural-Network Systems. CoRR (2024)
Philip Groet, Joost Hoozemans, Andreas Grapentin, Felix Eberhardt, Zaid Al-Ars, H. Peter Hofstee
Leveraging Apache Arrow for Zero-copy, Zero-serialization Cluster Shared Memory. CoRR (2024)
Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, H. Peter Hofstee
OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications. SC Workshops (2023)
Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
Tydi-lang: A Language for Typed Streaming Hardware. SC Workshops (2023)
Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. CoRR (2023)
Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee
SaLoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs. CoRR (2023)
Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars
Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators. NorCAS (2023)
Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. VLDB Workshops (2023)
Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
Tydi-lang: A Language for Typed Streaming Hardware. CoRR (2022)
Yongding Tian, Zaid Al-Ars, H. Peter Hofstee
Tydi-lang: a language for typed streaming hardware - A manual for future Tydi-lang compiler developers. CoRR (2022)
Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee
SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs. IPDPS (2022)
Tanveer Ahmad, Chengxin Ma, Zaid Al-Ars, H. Peter Hofstee
Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight. ISPDC (2022)
Tanveer Ahmad, Zaid Al-Ars, H. Peter Hofstee
Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices. CoRR (2022)
Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
Improving Gradient Paths for Binary Convolutional Neural Networks. BMVC (2022)
Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
An Attention Module for Convolutional Neural Networks. ICANN (1) (2021)
Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow. J. Signal Process. Syst. 93 (5) (2021)
Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. CoRR (2021)
Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee
Low Latency and High Throughput Write-Ahead Logging Using CAPI-Flash. IEEE Trans. Cloud Comput. 9 (3) (2021)
Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. IJCAI (2021)
Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
An Attention Module for Convolutional Neural Networks. CoRR (2021)
Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation. MICRO (2020)
Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic. J. Signal Process. Syst. 92 (9) (2020)
Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution. IEEE Access 8 (2020)
Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee
In-memory database acceleration on FPGAs: a survey. VLDB J. 29 (1) (2020)
Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks. CoRR (2020)
Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams. IEEE Micro 40 (4) (2020)
Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee
Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework. BMC Genom. 21 (S-10) (2020)
Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
NASB: Neural Architecture Search for Binary Convolutional Neural Networks. CoRR (2020)
Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
NASB: Neural Architecture Search for Binary Convolutional Neural Networks. IJCNN (2020)
Johan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang, Zaid Al-Ars, H. Peter Hofstee
Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA. FPT (2020)
Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. FPL (2019)
Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
Refine and Recycle: A Method to Increase Decompression Parallelism. ASAP (2019)
Mayoore Jaiswal, H. Peter Hofstee, Valerie Chen, Suvadip Paul, Rogério Feris, Frank Liu, Anupama Jagannathan, Anne Gattiker, Inseok Hwang, Jinho Lee, Matthew Tong, Sahil Dureja, Soham Shah
Video-Text Compliance: Activity Verification Based on Natural Language Instructions. ICCV Workshops (2019)
Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model. FCCM (2019)
Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. ARC (2019)
Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee
CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra. IEEE CLOUD (2018)
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu
Giving Text Analytics a Boost. CoRR (2018)
Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. 111 (2018)
Gordon C. Fossum, Ting Wang, H. Peter Hofstee
A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys. ISC Workshops (2018)
Jian Fang, Jianyu Chen, Zaid Al-Ars, H. Peter Hofstee, Jan Hidders
A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress. CODES+ISSS (2018)
Jian Fang, Jinho Lee, H. Peter Hofstee, Jan Hidders
Analyzing In-Memory Hash Join: Granularity Matters. ADMS@VLDB (2017)
Hamid Mushtaq, Frank Liu, Carlos Costa, Gang Liu, H. Peter Hofstee, Zaid Al-Ars
SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale. BCB (2017)
Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. 10 (12) (2017)
H. Peter Hofstee, Patrick Lysaght, Dirk van den Heuvel
RAW 2016 Keynotes. IPDPS Workshops (2016)
Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. IEEE Comput. Archit. Lett. 15 (1) (2016)
Zhen Jia, Chao Xue, Guancheng Chen, Jianfeng Zhan, Lixin Zhang, Yonghua Lin, H. Peter Hofstee
Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading. PACT (2016)
Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee
Optimized Durable Commitlog for Apache Cassandra Using CAPI-Flash. CLOUD (2016)
Fadi H. Gebara, H. Peter Hofstee, Kevin J. Nowka
Second-Generation Big Data Systems. Computer 48 (1) (2015)
Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam
Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. 59 (2/3) (2015)
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi
Giving Text Analytics a Boost. IEEE Micro 34 (4) (2014)
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
Hardware-accelerated text analytics. Hot Chips Symposium (2014)
H. Peter Hofstee, Guan-Cheng Chen, Fadi H. Gebara, Kevin Hall, Jay Herring, Damir A. Jamsek, Jian Li, Yan Li, Juwei Shi, Peter Wai Yee Wong
Understanding system design for Big Data workloads. IBM J. Res. Dev. 57 (3/4) (2013)
Anne E. Gattiker, Fadi H. Gebara, H. Peter Hofstee, J. D. Hayes, A. Hylick
Big Data text-oriented benchmark creation for Hadoop. IBM J. Res. Dev. 57 (3/4) (2013)
John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. IBM J. Res. Dev. 57 (6) (2013)
H. Peter Hofstee
The Next 25 Years of Computer Architecture? Euro-Par Workshops (2009)
Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops (2009)
Bernard D. Frischer, Dean Abernathy, Gabriele Guidi, Joel Myers, Cassie Thibodeau, Antonio Salvemini, Pascal Müller, H. Peter Hofstee, Barry Minor
Rome Reborn. SIGGRAPH New Tech Demos (2008)
Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny
Cell Broadband Engine Processor Design Methodology. CICC (2007)
Kanna Shimizu, H. Peter Hofstee, John S. Liberty
Cell Broadband Engine processor vault security architecture. IBM J. Res. Dev. 51 (5) (2007)
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51 (5) (2007)
H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko
Preface. IBM J. Res. Dev. 51 (5) (2007)
Michael T. Clark, H. Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler
The future of multi-core technologies. CLUSTER (2007)
Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki
Synergistic Processing in Cell's Multicore Architecture. IEEE Micro 26 (2) (2006)
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, Fellow, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41 (1) (2006)
Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41 (1) (2006)
H. Peter Hofstee
Invited speakers II - Real-time supercomputing and technology for games and entertainment. SC (2006)
Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC (2006)
James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David J. Shippy
Introduction to the Cell multiprocessor. IBM J. Res. Dev. 49 (4-5) (2005)
H. Peter Hofstee, Michael N. Day
Hardware and software architectures for the CELL processor. CODES+ISSS (2005)
H. Peter Hofstee
Communication and Synchronization in the Cell Processor - Invited Talk. CPA (2005)
Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. CICC (2005)
H. Peter Hofstee
Power Efficient Processor Architecture and The Cell Processor. HPCA (2005)
H. Peter Hofstee
Power-Constrained Microprocessor Design. ICCD (2002)
H. Peter Hofstee, Jun Sawada
Derivation of a rotator circuit with homogeneous interconnect. Inf. Process. Lett. 77 (2-4) (2001)
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
Timed circuit verification using TEL structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
"Timing closure by design, " a high frequency microprocessor design methodology. DAC (2000)
David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44 (6) (2000)
H. Peter Hofstee, Kevin J. Nowka
Beyond 1 GHz. CICC (1999)
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC (1999)
David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS (1998)
H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi
Designing for a gigahertz [guTS integer processor]. IEEE Micro 18 (3) (1998)
Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki
A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD (1998)
Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33 (11) (1998)
Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo
Design methodology for a 1.0 GHz microprocessor. ICCD (1998)
Kevin J. Nowka, H. Peter Hofstee
Circuits and Microarchitecture for Gigahertz VLSI Designs. ARVLSI (1997)
H. Peter Hofstee
Distributing a Class of Sequential Programs. Sci. Comput. Program. 22 (1-2) (1994)
H. Peter Hofstee
Distributing a Class of Sequential Programs. MPC (1992)
H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut
A Distributed Implementation of a Task Pool. Research Directions in High-Level Parallel Programming Languages (1991)
H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut
Distributed Sorting. Sci. Comput. Program. 15 (2-3) (1990)