Verification of Delayed-Reset Domino Circuits Using ATACS.

Wendy Belluomini Chris J. Myers H. Peter Hofstee

Published in: ASYNC (1999)

Keyphrases

asynchronous circuits
high speed
model checking
delay insensitive
digital circuits
vlsi circuits
databases
reinforcement learning
face verification
formal analysis
formal verification
quantum computing
high level synthesis
functional verification