Kubilay Atasu

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 28

Top Topics

Machine Learning

Parallel Algorithm

Top Venues

J. Signal Process. Syst.

IPDPS Workshops

Publications

Jovan Blanusa, Maximo Cravero Baraja, Andreea Anghel, Luc von Niederhäusern, Erik Altman, Haris Pozidis, Kubilay Atasu
Graph Feature Preprocessor: Real-time Extraction of Subgraph-based Features from Transaction Graphs. CoRR (2024)
Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik R. Altman, Roger Wattenhofer, Kubilay Atasu
Provably Powerful Graph Neural Networks for Directed Multigraphs. AAAI (2024)
Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik Altman, Roger Wattenhofer, Kubilay Atasu
Provably Powerful Graph Neural Networks for Directed Multigraphs. CoRR (2023)
Jovan Blanusa, Kubilay Atasu, Paolo Ienne
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR (2023)
Erik Altman, Jovan Blanusa, Luc von Niederhäusern, Beni Egressy, Andreea Anghel, Kubilay Atasu
Realistic Synthetic Financial Transactions for Anti-Money Laundering Models. NeurIPS (2023)
Erik Altman, Béni Egressy, Jovan Blanusa, Kubilay Atasu
Realistic Synthetic Financial Transactions for Anti-Money Laundering Models. CoRR (2023)
Jovan Blanusa, Kubilay Atasu, Paolo Ienne
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. 10 (3) (2023)
Jovan Blanusa, Paolo Ienne, Kubilay Atasu
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR (2022)
Jovan Blanusa, Paolo Ienne, Kubilay Atasu
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA (2022)
Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis
Tera-scale coordinate descent on GPUs. Future Gener. Comput. Syst. 108 (2020)
Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. 13 (11) (2020)
Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops (2020)
Kubilay Atasu, Thomas Mittelholzer
Linear-Complexity Data-Parallel Earth Mover's Distance Approximations. ICML (2019)
Michail Vlachos, Celestine Dünner, Reinhard Heckel, Vassilios G. Vassiliadis, Thomas P. Parnell, Kubilay Atasu
Addressing Interpretability and Cold-Start in Matrix Factorization for Recommender Systems. IEEE Trans. Knowl. Data Eng. 31 (7) (2019)
Kubilay Atasu, Thomas Mittelholzer
Low-Complexity Data-Parallel Earth Mover's Distance Approximations. CoRR (2018)
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu
Giving Text Analytics a Boost. CoRR (2018)
Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. 111 (2018)
Kubilay Atasu, Vasileios Vasileiadis, Michail Vlachos
Faster Text Similarity Using a Linear-Complexity Relaxed Word Mover's Distance. ERCIM News 2018 (112) (2018)
Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker
Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. 88 (2) (2017)
Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi
Linear-Complexity Relaxed Word Mover's Distance with GPU Acceleration. CoRR (2017)
Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis
Understanding and optimizing the performance of distributed machine learning applications on apache spark. IEEE BigData (2017)
Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis
Large-Scale Stochastic Learning Using GPUs. IPDPS Workshops (2017)
Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Michail Vlachos, Haralampos Pozidis
High-Performance Recommender System Training Using Co-Clustering on CPU/GPU Clusters. ICPP (2017)
Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis
Large-Scale Stochastic Learning using GPUs. CoRR (2017)
Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi
Linear-complexity relaxed word Mover's distance with GPU acceleration. IEEE BigData (2017)
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama
Annotation-based finite-state transducers on reconfigurable devices. FPL (2016)
Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis
High-Performance Distributed Machine Learning using Apache SPARK. CoRR (2016)
Kubilay Atasu
Feature-rich Regular Expression Matching Accelerator for Text Analytics. J. Signal Process. Syst. 85 (3) (2016)
Kubilay Atasu
Leftmost longest regular expression matching in reconfigurable logic. FPT (2015)
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi
Giving Text Analytics a Boost. IEEE Micro 34 (4) (2014)
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
Hardware-accelerated text analytics. Hot Chips Symposium (2014)
Melissa C. Smith, Kubilay Atasu
Guest Editorial: Application Specific Processors and Architectures. J. Signal Process. Syst. 77 (1-2) (2014)
Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu
Compiling text analytics queries to FPGAs. FPL (2014)
Kubilay Atasu
Resource-efficient regular expression matching architecture for text analytics. ASAP (2014)
Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss
Hardware-accelerated regular expression matching for high-throughput text analytics. FPL (2013)
Kubilay Atasu, Florian Dörfler, Jan van Lunteren, Christoph Hagleitner
Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor. IPDPS (2013)
Kubilay Atasu, Raphael Polig, Jonathan Rohrer, Christoph Hagleitner
Exploring the design space of programmable regular expression matching accelerators. J. Syst. Archit. 59 (10-D) (2013)
Raphael Polig, Kubilay Atasu, Christoph Hagleitner
Token-based dictionary pattern matching for text analytics. FPL (2013)
Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator. MICRO (2012)
Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar
FISH: Fast Instruction SyntHesis for Custom Processors. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Joseph Reddington, Kubilay Atasu
Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 20 (12) (2012)
Mitra Purandare, Kubilay Atasu, Christoph Hagleitner
Proving correctness of regular expression accelerators. DAC (2012)
Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner
Memory-efficient distribution of regular expressions for fast deep packet inspection. CODES+ISSS (2009)
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
Fast custom instruction identification by convex subgraph enumeration. ASAP (2008)
Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk
CHIPS: Custom Hardware Instruction Processor Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
Optimizing instruction-set extensible processors under data bandwidth constraints. DATE (2007)
Wayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer
Towards optimal custom instruction processors. Hot Chips Symposium (2006)
Laura Pozzi, Kubilay Atasu, Paolo Ienne
Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (7) (2006)
Kubilay Atasu, Günhan Dündar, Can C. Özturan
An integer linear programming approach for identifying instruction-set extensions. CODES+ISSS (2005)
Kubilay Atasu, Luca Breveglieri, Marco Macchetti
Efficient AES implementations for ARM based platforms. SAC (2004)
Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
Introduction of local memory elements in instruction set extensions. DAC (2004)
Kubilay Atasu, Laura Pozzi, Paolo Ienne
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. 31 (6) (2003)
Kubilay Atasu, Laura Pozzi, Paolo Ienne
Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC (2003)