Steven Derrien

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 34

Top Topics

Memory Bandwidth

Special Section

Parallel Implementation

Partitioning Algorithm

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Jean-Michel Gorius, Simon Rokicki, Steven Derrien
A Unified Memory Dependency Framework for Speculative High-Level Synthesis. CC (2024)
Corentin Ferry, Nicolas Derumigny, Steven Derrien, Sanjay V. Rajopadhye
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. CoRR (2024)
Louis Narmour, Steven Derrien, Sanjay V. Rajopadhye
Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations. PACT (2023)
Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (5) (2023)
Corentin Ferry, Steven Derrien, Sanjay V. Rajopadhye
An Irredundant Decomposition of Data Flow with Affine Dependences. CoRR (2023)
Sara Sadat Hoseininasab, Caroline Collange, Steven Derrien
Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis. ARC (2023)
Jean-Michel Gorius, Simon Rokicki, Steven Derrien
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis. IEEE Micro 42 (5) (2022)
Jean-Michel Gorius, Simon Rokicki, Steven Derrien
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. FPT (2022)
Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye
Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout. CoRR (2022)
Frank Hannig, Steven Derrien
Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. 94 (9) (2022)
Corentin Ferry, Steven Derrien, Sanjay V. Rajopadhye
Maximal Atomic irRedundant Sets: a Usage-based Dataflow Partitioning Algorithm. CoRR (2022)
Steven Derrien, Thibaut Marty, Simon Rokicki, Tomofumi Yuki
Toward Speculative Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)
Yohann Uguen, Florent de Dinechin, Victor Lezaud, Steven Derrien
Application-Specific Arithmetic in High-Level Synthesis Tools. ACM Trans. Archit. Code Optim. 17 (1) (2020)
Thibaut Marty, Tomofumi Yuki, Steven Derrien
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Simon Rokicki, Erven Rohou, Steven Derrien
Aggressive Memory Speculation in HW/SW Co-Designed Machines. DATE (2019)
Benjamin Rouxel, Stefanos Skalistis, Steven Derrien, Isabelle Puaut
Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. ECRTS (2019)
Simon Reder, Fabian Kempf, Harald Bucher, Jürgen Becker, Panayiotis Alefragis, Nikolaos S. Voros, Stefanos Skalistis, Steven Derrien, Isabelle Puaut, Oliver Oey, Timo Stripf, Christian Ferdinand, Clément David, Peer Ulbig, David Müller, Umut Durak
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. J. Aerosp. Inf. Syst. 16 (11) (2019)
Simon Rokicki, Erven Rohou, Steven Derrien
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (10) (2019)
Mickaël Dardaillon, Stefanos Skalistis, Isabelle Puaut, Steven Derrien
Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation. RTSS (2019)
Thibaut Marty, Tomofumi Yuki, Steven Derrien
Enabling Overclocking Through Algorithm-Level Error Detection. FPT (2018)
Thomas Lefeuvre, Imen Fassi, Christoph Cullmann, Gernot Gebhard, Emin-Koray Kasnakli, Isabelle Puaut, Steven Derrien
Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction. DATE (2018)
Simon Rokicki, Erven Rohou, Steven Derrien
Supporting runtime reconfigurable VLIWs cores through dynamic binary translation. DATE (2018)
Isabelle Puaut, Mickaël Dardaillon, Christoph Cullmann, Gernot Gebhard, Steven Derrien
Fine-Grain Iterative Compilation for WCET Estimation. WCET (2018)
Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker
Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. 88 (2) (2017)
Ali Hassan El Moussawi, Steven Derrien
Superword level parallelism aware word length optimization. DATE (2017)
Benjamin Rouxel, Steven Derrien, Isabelle Puaut
Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE (2017)
Yohann Uguen, Florent de Dinechin, Steven Derrien
A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. FCCM (2017)
Simon Rokicki, Erven Rohou, Steven Derrien
Hardware-accelerated dynamic binary translation. DATE (2017)
Yohann Uguen, Florent de Dinechin, Steven Derrien
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. FPL (2017)
Gaël Deest, Tomofumi Yuki, Sanjay V. Rajopadhye, Steven Derrien
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. FPL (2017)
Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Steven Derrien
Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures. MCSoC (2016)
Ali Hassan El Moussawi, Steven Derrien
Demo: SLP-aware word length optimization. DASIP (2016)
Nicolas Estibals, Gaël Deest, Ali Hassan El Moussawi, Steven Derrien
System level synthesis for virtual memory enabled hardware threads. DATE (2016)
Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton, Alexandre Cornu, Dominique Lavenier
Combining execution pipelines to improve parallel implementation of HMMER on FPGA. Microprocess. Microsystems 39 (7) (2015)
Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux
Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. FCCM (2014)
Gaël Deest, Tomofumi Yuki, Olivier Sentieys, Steven Derrien
Toward scalable source level accuracy analysis for floating-point to fixed-point conversion. ICCAD (2014)
Anne-Marie Chana, Patrice Quinton, Steven Derrien
Component reuse methodology for multi-clock Data-Flow parallel embedded Systems. ARIMA J. 18 (2014)
Antoine Floch, Tomofumi Yuki, Ali El Moussawi, Antoine Morvan, Kevin J. M. Martin, Maxime Naullet, Mythri Alle, Ludovic L'Hours, Nicolas Simon, Steven Derrien, François Charot, Christophe Wolinski, Olivier Sentieys
GeCoS: A framework for prototyping custom hardware design flows. SCAM (2013)
Tomofumi Yuki, Antoine Morvan, Steven Derrien
Derivation of efficient FSM from loop nests. FPT (2013)
Antoine Morvan, Steven Derrien, Patrice Quinton
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Wuliang Sun, Benoît Combemale, Steven Derrien, Robert B. France
Using Model Types to Support Contract-Aware Model Substitutability. ECMFA (2013)
Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, Thomas Perschke
Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsystems 37 (8-C) (2013)
Mythri Alle, Antoine Morvan, Steven Derrien
Runtime dependency analysis for loop pipelining in high-level synthesis. DAC (2013)
Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations. DSD (2013)
Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Ménard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD (2012)
Jean-Marc Jézéquel, Benoît Combemale, Steven Derrien, Clement Guy, Sanjay V. Rajopadhye
Bridging the chasm between MDE and the world of compilation. Softw. Syst. Model. 11 (4) (2012)
Patrice Quinton, Anne-Marie Chana, Steven Derrien
Efficient hardware implementation of data-flow parallel embedded systems. ICSAMOS (2012)
Clement Guy, Benoît Combemale, Steven Derrien, Jim Steel, Jean-Marc Jézéquel
On Model Subtyping. ECMFA (2012)
Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Jordy Potman, Kim Sunesen, Steven Derrien, Olivier Sentieys, Jürgen Becker
A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. CSE (2012)
George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Ménard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas
From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS (2012)
Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien
A semiempirical model for wakeup time estimation in power-gated logic clusters. DAC (2012)
Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Ménard, Olivier Sentieys, Diana Göhringer, Thomas Perschke
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC (2012)
Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow. ACM Trans. Design Autom. Electr. Syst. 17 (1) (2012)
Antoine Morvan, Steven Derrien, Patrice Quinton
Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion. FPT (2011)
Antoine Floch, Tomofumi Yuki, Clement Guy, Steven Derrien, Benoît Combemale, Sanjay V. Rajopadhye, Robert B. France
Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far? MoDELS (2011)
Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien
Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters. VLSI Design (2011)
V. Basupalli, Tomofumi Yuki, Sanjay V. Rajopadhye, Antoine Morvan, Steven Derrien, Patrice Quinton, David Wonnacott
ompVerify: Polyhedral Analysis for the OpenMP Programmer. IWOMP (2011)
Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien
A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. J. Low Power Electron. 7 (4) (2011)
Alexandre Cornu, Steven Derrien, Dominique Lavenier
HLS Tools for FPGA: Faster Development with Better Performance. ARC (2011)
Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton
Accelerating HMMER on FPGA using parallel prefixes and reductions. FPT (2010)
Steven Derrien, Patrice Quinton
Hardware Acceleration of HMMER on FPGAs. J. Signal Process. Syst. 58 (1) (2010)
Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. DAC (2010)
Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. DSD (2010)
Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
Ultra Low-power FSM for Control Oriented Applications. ISCAS (2009)
Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. 3 (3) (2008)
Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. ARC (2007)
Steven Derrien, Patrice Quinton
Parallelizing HMMER for Hardware Acceleration on FPGAs. ASAP (2007)
Auguste Noumsi, Steven Derrien, Patrice Quinton
Acceleration of a content-based image-retrieval application on the RDISK cluster. IPDPS (2006)
Stéphane Guyetant, Mathieu Giraud, Ludovic L'Hours, Steven Derrien, Stéphane Rubini, Dominique Lavenier, Frédéric Raimbault
Cluster of re-configurable nodes for scanning large genomic banks. Parallel Comput. 31 (1) (2005)
Alain Darte, Steven Derrien, Tanguy Risset
Hardware/Software Interface for Multi-Dimensional Processor Arrays. ASAP (2005)
Dominique Lavenier, Stéphane Guyetant, Steven Derrien, Stéphane Rubini
A Reconfigurable Parallel Disk System for Filtering Genomic Banks. Engineering of Reconfigurable Systems and Algorithms (2003)
Sanjay V. Rajopadhye, Steven Derrien
Energy/Power Estimation of Regular Processor Arrays. ISSS (2002)
Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
Combining Instruction and Loop Level Parallelism for FPGAs. FCCM (2001)
Steven Derrien, Sanjay V. Rajopadhye
Loop Tiling for Reconfigurable Accelerators. FPL (2001)
Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS (2001)
Steven Derrien, Tanguy Risset
Interfacing compiled FPGA programs: the MMAlpha approach. PDPTA (2000)
Steven Derrien, Kurt Konolige
Approximating a Single Viewpoint in Panoramic Imaging Devices. ICRA (2000)
Steven Derrien, Sanjay V. Rajopadhye
FCCMS and the Memory Wall. FCCM (2000)
Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC (2000)