Loop Tiling for Reconfigurable Accelerators.
Steven DerrienSanjay V. RajopadhyePublished in: FPL (2001)
Keyphrases
- field programmable gate array
- low cost
- hardware implementation
- single chip
- reconfigurable architecture
- general purpose
- computing systems
- digital signal
- fine grain
- feedback loop
- neural network
- embedded systems
- image processing algorithms
- computing platform
- website
- image processing
- multi objective evolutionary
- parallel computing
- database systems
- knowledge base
- learning algorithm