Accelerating HMMER on FPGA using parallel prefixes and reductions.
Naeem AbbasSteven DerrienSanjay V. RajopadhyePatrice QuintonPublished in: FPT (2010)
Keyphrases
- parallel hardware
- real time
- parallel processing
- parallel architecture
- hardware implementation
- variable length
- field programmable gate array
- artificial intelligence
- high speed
- pipelined architecture
- shared memory
- parallel programming
- distributed memory machines
- database
- systolic array
- real time image processing
- software implementation
- hardware design
- distributed memory
- parallel computation
- data acquisition
- image processing