Ed F. Deprettere

Publication Activity (10 Years)

Years Active: 1982-2012
Publications (10 Years): 0

Top Venues

ICSAMOS

Publications

Ed F. Deprettere
Special session on "aspects of Cyber-Physical Systems". ICSAMOS (2012)
Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere
USHA: Unified software and hardware architecture for video decoding. SASP (2011)
Ed F. Deprettere, Ana Lucia Varbanescu
Introduction to Mastering Cell BE and GPU Execution Platforms. SAMOS (2009)
Dmitry Nadezhkin, Sjoerd Meijer, Todor P. Stefanov, Ed F. Deprettere
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell. SAMOS (2009)
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
Systematic and Automated Multiprocessor System Design, Programming, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Andy D. Pimentel, Todor P. Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. SAMOS (2008)
Bin Jiang, Ed F. Deprettere, Bart Kienhuis
Hierarchical run time deadlock detection in process networks. SiPS (2008)
Hristo Nikolov, Mark Thompson, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere
Daedalus: toward composable multimedia MP-SoC design. DAC (2008)
Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. 3 (3) (2008)
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM. EURASIP J. Embed. Syst. 2008 (2008)
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. FPL (2007)
Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Trans. Signal Process. 55 (6-2) (2007)
Ed F. Deprettere, Roger F. Woods, Ingrid Verbauwhede, Erwin A. de Kock
Transforming Signal Processing Applications into Parallel Implementations. EURASIP J. Adv. Signal Process. 2007 (2007)
Mark Thompson, Hristo Nikolov, Todor P. Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. CODES+ISSS (2007)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embed. Comput. Syst. 6 (2) (2007)
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. FPL (2006)
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
Multi-processor system design with ESPAM. CODES+ISSS (2006)
Ed F. Deprettere, Todor P. Stefanov, Shuvra S. Bhattacharyya, Mainak Sen
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. ASAP (2006)
Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
Requirements for Interfacing IP-Components in Re-configurable Platforms. J. VLSI Signal Process. 43 (2-3) (2006)
Jérôme Lemaitre, Ed F. Deprettere
FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. Euro-Par (2006)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
Solving Out-of-Order Communication in Kahn Process Networks. J. VLSI Signal Process. 40 (1) (2005)
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Expression Synthesis in Process Networks generated by LAURA. ASAP (2005)
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters. FCCM (2005)
Mihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos
FPL-3E: Towards Language Support for Reconfigurable Packet Processing. SAMOS (2005)
Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
Behavioral specification of control interface for signal processing applications. ASAP (2005)
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Communication Synthesis in a multiprocessor environment. FPL (2005)
Todor P. Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE (2004)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES (2004)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP (2004)
Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
On the (Re-)Use of IP-Components in Re-configurable Platforms. SAMOS (2004)
Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin A. de Kock
Communication Optimization in Compaan Process Networks. SAMOS (2004)
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL (2004)
Sylvain Alliot, Ed F. Deprettere
Architecture Exploration of a Large Scale System. IEEE International Workshop on Rapid System Prototyping (2004)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
Translating affine nested-loop programs to process networks. CASES (2004)
Laurentiu Nicolae, Ed F. Deprettere
Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. SAMOS (2004)
Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. DATE (2003)
Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
Analysis of joint angle-frequency estimation using ESPRIT. IEEE Trans. Signal Process. 51 (5) (2003)
Todor P. Stefanov, Ed F. Deprettere
Deriving process networks from weakly dynamic applications in system-level design. CODES+ISSS (2003)
Bart Kienhuis, Ed F. Deprettere
Modeling Stream-Based Applications Using the SBF Model of Computation. J. VLSI Signal Process. 34 (3) (2003)
Claudiu Zissulescu, Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
Laura: Leiden Architecture Research and Exploration Tool. FPL (2003)
Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere
Context-Aware Process Networks. ASAP (2003)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP (2002)
Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis
Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges (2002)
Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES (2002)
Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges (2002)
Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere
Compilation From Matlab to Process Networks Realized in FPGA. Des. Autom. Embed. Syst. 7 (4) (2002)
Ed F. Deprettere, Bart Kienhuis, Richard L. Walke
Preface. Des. Autom. Embed. Syst. 7 (4) (2002)
Jun Ma, Keshab K. Parhi, Ed F. Deprettere
A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms. IEEE Trans. Signal Process. 49 (2) (2001)
Paul Lieverse, Todor P. Stefanov, Pieter van der Wolf, Ed F. Deprettere
System Level Design with Spade: an M-JPEG Case Study. ICCAD (2001)
Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. J. VLSI Signal Process. 29 (3) (2001)
Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
Exploring Embedded-Systems Architectures with Artemis. Computer 34 (11) (2001)
Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
A trace transformation technique for communication refinement. CODES (2001)
Kees-Jan van der Kolk, Jeong-A Lee, Ed F. Deprettere
A Floating Point Vectoring Algorithm Based on Fast Rotations. J. VLSI Signal Process. 25 (2) (2000)
Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES (2000)
Jun Ma, Keshab K. Parhi, Ed F. Deprettere
Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming. IEEE Trans. Signal Process. 48 (8) (2000)
Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
Analysis of ESPRIT based joint angle-frequency estimation. ICASSP (2000)
Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis
Deriving Process Networks from Nested Loop Algorithms. Parallel Process. Lett. 10 (2/3) (2000)
Gerben J. Hekstra, Ed F. Deprettere, Jeong-A Lee
Guest Editor's Introduction. J. VLSI Signal Process. 25 (2) (2000)
Jun Ma, Keshab K. Parhi, Gerben J. Hekstra, Ed F. Deprettere
Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations. IEEE Trans. Signal Process. 48 (9) (2000)
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP (2000)
Jun Ma, Keshab K. Parhi, Ed F. Deprettere
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations. ISCAS (3) (1999)
Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
Multiresolution ESPRIT algorithm. IEEE Trans. Signal Process. 47 (6) (1999)
Kees-Jan van der Kolk, Ed F. Deprettere, Jeong-A Lee
A Floating Point Vectoring Algorithm Based on Fast Rotations. EUROMICRO (1999)
Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock
A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. J. VLSI Signal Process. 22 (1) (1999)
Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
Joint angle-frequency estimation using multi-resolution ESPRIT. ICASSP (1998)
Jun Ma, Keshab K. Parhi, Ed F. Deprettere
Pipelined CORDIC based QRD-MVDR adaptive beamforming. ICASSP (1998)
Joost Nieuwenhuijse, Richard Heusdens, Ed F. Deprettere
Robust exponential modeling of audio signals. ICASSP (1998)
Laurens Bierens, Ed F. Deprettere
Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures. J. VLSI Signal Process. 18 (1) (1998)
W. Bastiaan Kleijn, Huimin Yang, Ed F. Deprettere
Waveform interpolation coding with pitch-spaced subbands. ICSLP (1998)
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
The construction of a retargetable simulator for an architecture template. CODES (1998)
Aweke N. Lemma, W. Bastiaan Kleijn, Ed F. Deprettere
Quantization using wavelet based temporal decomposition of the LSF. EUROSPEECH (1997)
Vincent van de Laar, W. Bastiaan Kleijn, Ed F. Deprettere
Perceptual entropy rate estimates for the phonemes of American English. ICASSP (1997)
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP (1997)
Gerben J. Hekstra, Ed F. Deprettere
Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation. IEEE Symposium on Computer Arithmetic (1997)
Jun Ma, Keshab K. Parhi, Ed F. Deprettere
Pipelining of cordic based IIR digital filters. ICASSP (1997)
Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma
A strategy for determining a Jacobi specific dataflow processor. ASAP (1997)
Aweke N. Lemma, Ed F. Deprettere
State space behavior in time-varying biorthogonal filter banks. EUSIPCO (1996)
Marc Moonen, Ed F. Deprettere
A fully pipelined RLS-based array for channel equalization. J. VLSI Signal Process. 14 (1) (1996)
Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere
Jacobi-Specific Processor Arrays. ASAP (1996)
Aweke N. Lemma, Ed F. Deprettere
Two-sided controlled transition in biorthogonal time-varying filter banks. IEEE Signal Process. Lett. 3 (2) (1996)
Laurens Bierens, Ed F. Deprettere
Engineering multirate convolutions for radar imaging. ICASSP (1996)
Li-Sheng Shen, Ed F. Deprettere, Patrick M. Dewilde
A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading. Comput. Graph. 19 (2) (1995)
Marc Moonen, Ed F. Deprettere, Ian K. Proudler, John G. McWhirter
On the derivation of parallel filter structures for adaptive eigenvalue and singular value decompositions. ICASSP (1995)
Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere
Scalable parallel processor array for Jacobi-type matrix computations. Integr. 20 (1) (1995)
Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS (1994)
Marc Moonen, Filiep J. Vanpoucke, Ed F. Deprettere
Parallel and adaptive high-resolution direction finding. IEEE Trans. Signal Process. 42 (9) (1994)
Filiep Vanpoucke, Marc Moonen, Ed F. Deprettere
Direction finding of multiple wide-band emitters using state-space modeling. Signal Process. 40 (1) (1994)
Ed F. Deprettere, Gerben J. Hekstra, Li-Sheng Shen, Jichun Bu, Gerrit Boersma
A parallel system for photo realistic artificial scene rendering. ASAP (1994)
Ed F. Deprettere, Hylke W. van Dijk, Gerben J. Hekstra
A 'Jacobi' signal processing unit for time-adaptive SVD. ICASSP (2) (1994)
Alle-Jan van der Veen, Ed F. Deprettere, A. Lee Swindlehurst
Subspace-based signal analysis using singular value decomposition. Proc. IEEE 81 (9) (1993)
Gerben J. Hekstra, Ed F. Deprettere
Floating point Cordic. IEEE Symposium on Computer Arithmetic (1993)
Ed F. Deprettere
Example of combined algorithm development and architecture design. Integr. 16 (3) (1993)
Ed F. Deprettere, Richard Heusdens, Hendrik Theunis
Subband filtering: Cordic modulation and systolic quadrature mirror filter tree. ASAP (1993)
Alle-Jan van der Veen, P. Bas Ober, Ed F. Deprettere
Azimuth and elevation computation in high resolution DOA estimation. IEEE Trans. Signal Process. 40 (7) (1992)
Emmanuel D. Frimout, Johannes N. Driessen, Ed F. Deprettere
Parallel architecture for a pel-recursive motion estimation algorithm. IEEE Trans. Circuits Syst. Video Technol. 2 (2) (1992)
Emmanuel D. Frimout, Johannes N. Driessen, Ed F. Deprettere
Parallel architecture for a pel-recursive motion estimation algorithm. ASAP (1992)
Li-Sheng Shen, Ed F. Deprettere
A Parallel-Pipelined Multiprocessor System for the Radiosity Method. Eurographics Workshop on Graphics Hardware (1992)
P. Bas Ober, Ed F. Deprettere, Alle-Jan van der Veen
Efficient methods to compute azimuth and elevation in high resolution DOA estimation. ICASSP (1991)
A. J. van der Hoeven, Ed F. Deprettere, P. van Prooijen, Patrick M. Dewilde
A hardware design system based on object-oriented principles. EURO-DAC (1991)
Alle-Jan van der Veen, Ed F. Deprettere
Parallel VLSI matrix pencil algorithm for high resolution direction finding. IEEE Trans. Signal Process. 39 (2) (1991)

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Publication Activity (10 Years)

Top Venues

Ed F. Deprettere