Bart Kienhuis

Publication Activity (10 Years)

Years Active: 1997-2016
Publications (10 Years): 2

Top Topics

Heterogeneous Platforms

Highly Efficient

Transmission Electron Microscopy

Top Venues

IPDPS Workshops

Publications

Wouter van Teijlingen, Rene van Leuken, Carlo Galuzzi, Bart Kienhuis
Determining Performance Boundaries on High-Level System Specifications. SCOPES (2016)
Tsvetan Shoshkov, Todor P. Stefanov, Bart Kienhuis
Parametrized system level design: Real-time X-Ray image processing case study. ASAP (2016)
Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer
HEAP: A Highly Efficient Adaptive multi-Processor framework. Microprocess. Microsystems 37 (8-C) (2013)
Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer
HEAP: A Highly Efficient Adaptive Multi-processor Framework. DSD (2012)
Sven van Haastregt, Bart Kienhuis
Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations. ASAP (2012)
Ana Balevic, Bart Kienhuis
Scaling Data-Intensive Applications on Heterogeneous Platforms with Accelerators. IPDPS Workshops (2012)
Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations. MCSoC (2012)
Ana Balevic, Bart Kienhuis
A data parallel view on polyhedral process networks. SCOPES (2011)
Ana Balevic, Bart Kienhuis
KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks. SIGARCH Comput. Archit. News 39 (4) (2011)
Razvan Nane, Sven van Haastregt, Todor P. Stefanov, Bart Kienhuis, Vlad Mihai Sima, Koen Bertels
IP-XACT extensions for Reconfigurable Computing. ASAP (2011)
Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA (2011)
Sven van Haastregt, Eyal Halm, Bart Kienhuis
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems. DATE (2010)
Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki
Cool MPSoC programming. DATE (2010)
Barbara M. Chapman, Bart Kienhuis, Eduard Ayguadé, François Bodin, Oscar G. Plata, Eric Stotzer
Introduction. Euro-Par (2009)
Sven van Haastregt, Bart Kienhuis
Automated synthesis of streaming C applications to process networks in hardware. DATE (2009)
Bin Jiang, Ed F. Deprettere, Bart Kienhuis
Hierarchical run time deadlock detection in process networks. SiPS (2008)
Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. 3 (3) (2008)
Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Trans. Signal Process. 55 (6-2) (2007)
Sjoerd Meijer, Bart Kienhuis, Johan Walters, David Snuijf
Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor. SCOPES (2007)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embed. Comput. Syst. 6 (2) (2007)
Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock
Interactive presentation: A process splitting transformation for Kahn process networks. DATE (2007)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
Solving Out-of-Order Communication in Kahn Process Networks. J. VLSI Signal Process. 40 (1) (2005)
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Expression Synthesis in Process Networks generated by LAURA. ASAP (2005)
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Communication Synthesis in a multiprocessor environment. FPL (2005)
Todor P. Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE (2004)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES (2004)
Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. DATE (2004)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP (2004)
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL (2004)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
Translating affine nested-loop programs to process networks. CASES (2004)
Alexandru Turjan, Bart Kienhuis
Storage Management in Process Networks using the Lexicographically Maximal Preimage. ASAP (2003)
Bart Kienhuis, Ed F. Deprettere
Modeling Stream-Based Applications Using the SBF Model of Computation. J. VLSI Signal Process. 34 (3) (2003)
Claudiu Zissulescu, Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
Laura: Leiden Architecture Research and Exploration Tool. FPL (2003)
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP (2002)
Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis
Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges (2002)
Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES (2002)
Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges (2002)
Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere
Compilation From Matlab to Process Networks Realized in FPGA. Des. Autom. Embed. Syst. 7 (4) (2002)
Ed F. Deprettere, Bart Kienhuis, Richard L. Walke
Preface. Des. Autom. Embed. Syst. 7 (4) (2002)
Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES (2000)
Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis
Deriving Process Networks from Nested Loop Algorithms. Parallel Process. Lett. 10 (2/3) (2000)
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP (2000)
Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock
A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. J. VLSI Signal Process. 22 (1) (1999)
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
The construction of a retargetable simulator for an architecture template. CODES (1998)
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP (1997)