Kees A. Vissers

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 27

Top Topics

Adaptive Learning Rate

Hardware Implementation

Rapid Convergence

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Lois Orosa, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos, Juan Gómez-Luna, Michaela Blott, Kees A. Vissers, Onur Mutlu
EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators. IEEE Trans. Computers 73 (9) (2024)
Lois Orosa, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos, Juan Gómez-Luna, Michaela Blott, Kees A. Vissers, Onur Mutlu
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators. CoRR (2022)
Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang
FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. 15 (4) (2022)
Tobias Alonso, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, Kees A. Vissers
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning. ACM Trans. Reconfigurable Technol. Syst. 15 (2) (2022)
Alireza Khodamoradi, Kristof Denolf, Kees A. Vissers, Ryan Kastner
ASLR: An Adaptive Scheduler for Learning Rate. IJCNN (2021)
Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113 (2021)
Gábor Csordás, Kristof Denolf, Nicholas J. Fraser, Alessandro Pappalardo, Kees A. Vissers
Trainable Preprocessing for Reduced Precision Neural Networks. EUSIPCO (2021)
Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. CoRR (2020)
Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. CoRR (2020)
Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. HPEC (2020)
Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. ITC (2020)
Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR (2019)
Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong
Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. FPT (2019)
Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS (2019)
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT (2019)
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA (2019)
Kees A. Vissers
Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP). FPGA (2019)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM (2019)
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR (2019)
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR (2018)
Kees A. Vissers
Novel Neural Network Applications on New Python Enabled Platforms. FPT (2018)
Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers
: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Kees A. Vissers
Keynote 2: Versal: The new Xilinx Adaptive Compute Acceleration Platforms (ACAP). IA3@SC (2018)
Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR (2017)
Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC (2017)
Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA (2017)
Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR (2016)
Michaela Blott, Ling Liu, Kimon Karras, Kees A. Vissers
Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory. HotStorage (2015)
David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley
Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware. FCCM (2015)
Daniel Jiménez-González, Carlos Álvarez, Antonio Filgueras, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC. CoRR (2015)
Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers
A Hash Table for Line-Rate Data Processing. ACM Trans. Reconfigurable Technol. Syst. 8 (2) (2015)
Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
OmpSs@Zynq all-programmable SoC ecosystem. FPGA (2014)
Kimon Karras, Michaela Blott, Kees A. Vissers
High-Level Synthesis Case Study: Implementation of a Memcached Server. CoRR (2014)
Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek
Reconfigurable computing in the era of post-silicon scaling [panel discussion]. FCCM (2013)
Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers
Software-programmable digital pre-distortion on the Zynq SoC. VLSI-SoC (2013)
Michaela Blott, Kees A. Vissers
Dataflow architectures for 10Gbps line-rate key-value-stores. Hot Chips Symposium (2013)
Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers
A flexible hash table design for 10GBPS key-value stores on FPGAS. FPL (2013)
Michaela Blott, Kimon Karras, Ling Liu, Kees A. Vissers, Jeremia Bär, Zsolt István
Achieving 10Gbps Line-rate Key-value Stores with FPGAs. HotCloud (2013)
John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers
A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Hot Interconnects (2012)
Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera
Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. DATE (2011)
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA (2011)
Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro
Programming high performance signal processing systems in high level languages. FPGA (2010)
Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti
The wild west: conquest of complex hardware-dependent software design. DAC (2009)
Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers
Using C-to-gates to program streaming image processing kernels efficiently on FPGAs. FPL (2009)
Stephen Neuendorffer, Kees A. Vissers
Streaming Systems in FPGAs. SAMOS (2008)
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
Optimized Generation of Data-Path from C Codes for FPGAs CoRR (2007)
Kristof Denolf, Adrian Chirila-Rus, Paul R. Schumacher, Robert D. Turney, Kees A. Vissers, Diederik Verkest, Henk Corporaal
A Systematic Approach to Design Low-Power Video Codec Cores. EURASIP J. Embed. Syst. 2007 (2007)
Steve Douglass, Kees A. Vissers, Peter Alfke
The next generation 65-nm FPGA. Hot Chips Symposium (2006)
Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA (2005)
Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. J. VLSI Signal Process. 39 (3) (2005)
Paul R. Schumacher, Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Nick Fedele, Kees A. Vissers, Jan Bormans
A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications. ICIP (2) (2005)
Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers
Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs. FPL (2005)
Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers
Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications. IEEE International Workshop on Rapid System Prototyping (2005)
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
Optimized Generation of Data-Path from C Codes for FPGAs. DATE (2005)
Kees A. Vissers
Programming models and architectures for FPGA platforms. CASES (2004)
Kees A. Vissers
Programming Extremely Flexible Platforms. SAMOS (2004)
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
A quantitative analysis of the speedup factors of FPGAs over processors. FPGA (2004)
Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
Pel reconstruction on FPGA-augmented TriMedia. IEEE Trans. Very Large Scale Integr. Syst. 12 (6) (2004)
Kees A. Vissers
Parallel Processing Architectures for Reconfigurable Systems. DATE (2003)
Reinaldo A. Bergamaschi, Grant Martin, Wayne H. Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris
The future of system-level design: can we find the right solutions to the right problems at the right time? CODES+ISSS (2003)
Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang
Panel Title: Reconfigurable Computing - Different Perspectives. DATE (2003)
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. FCCM (2002)
Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
Field-Programmable Custom Computing Machines - A Taxonomy -. FPL (2002)
Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges (2002)
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. Embedded Processor Design Challenges (2002)
Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik
Developing Architectural Platforms: A Disciplined Approach. IEEE Des. Test Comput. 19 (6) (2002)
Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. J. VLSI Signal Process. 29 (3) (2001)
Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. FCCM (2001)
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. ICCD (2001)
Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers
The Future of Flexible HW Platform Architectures Panel Discussion. DATE (2000)
Erwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink
YAPI: application modeling for signal processing systems. DAC (2000)
Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers
An MPEG-2 decoder case study as a driver for a system level design methodology. CODES (1999)
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel
TriMedia CPU64 Architecture. ICCD (1999)
Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar
System level design and debug of high-performance embedded media systems (tutorial). ICCAD (1999)
A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans
TriMedia CPU64 Application Domain and Benchmark Suite. ICCD (1999)
Frans Sijstermans, Evert-Jan D. Pol, Bram Riemens, Kees A. Vissers, Selliah Rathnam, Gert Slavenburg
Design space exploration for future TriMedia CPUs. ICASSP (1998)
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
The construction of a retargetable simulator for an architecture template. CODES (1998)
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP (1997)
Kees A. Vissers
Trade-offs in the design of mixed hardware-software systems-a perspective from industry. CODES (1997)
Kees A. Vissers, Gerben Essink, Piet J. van Gerwen, P. J. M. Janssen, O. Popp, E. Riddersma, W. J. M. Smits, Harry J. M. Veendrick
Architecture and programming of two generations video signal processors. Microprocess. Microprogramming 41 (5-6) (1995)
Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers
Architecture and Programming of a VLIW Style Programmable Video Signal Processor. MICRO (1991)
Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers
Scheduling in Programmable Video Signal Processors. ICCAD (1991)