Joseph Zambreno

ORCID

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 45

Top Venues

Publications

Benjamin Welte, Joseph Zambreno
An FPGA Implementation of SipHash. IPDPS Workshops (2023)
Joshua R. Bertram, Joseph Zambreno, Peng Wei
Efficient Unmanned Aerial Systems Navigation With Collision Avoidance in Dense Urban Environments. IEEE Trans. Intell. Transp. Syst. 24 (8) (2023)
Joshua R. Bertram, Peng Wei, Joseph Zambreno
A Fast Markov Decision Process-Based Algorithm for Collision Avoidance in Urban Air Mobility. IEEE Trans. Intell. Transp. Syst. 23 (9) (2022)
Uchenna Ezeobi, Habeeb Olufowobi, Clinton Young, Joseph Zambreno, Gedare Bloom
Reverse Engineering Controller Area Network Messages Using Unsupervised Machine Learning. IEEE Consumer Electron. Mag. 11 (1) (2022)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP (2021)
Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113 (2021)
Clinton Young, Jordan Svoboda, Joseph Zambreno
Towards Reverse Engineering Controller Area Network Messages Using Machine Learning. WF-IoT (2020)
Saunak Saha, Henry Duwe, Joseph Zambreno
CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks. J. Signal Process. Syst. 92 (9) (2020)
Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno
ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. ASAP (2020)
Habeeb Olufowobi, Clinton Young, Joseph Zambreno, Gedare Bloom
SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing. IEEE Trans. Veh. Technol. 69 (2) (2020)
Joshua R. Bertram, Peng Wei, Joseph Zambreno
Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict. CoRR (2020)
Brian Kempa, Pei Zhang, Phillip H. Jones, Joseph Zambreno, Kristin Yvonne Rozier
Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. FORMATS (2020)
Saunak Saha, Henry Duwe, Joseph Zambreno
An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators. ASAP (2019)
Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR (2019)
Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS (2019)
Clinton Young, Habeeb Olufowobi, Gedare Bloom, Joseph Zambreno
Automotive Intrusion Detection Based on Constant CAN Message Frequencies Across Vehicle Driving Modes. AutoSec@CODASPY (2019)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM (2019)
Clinton Young, Joseph Zambreno, Habeeb Olufowobi, Gedare Bloom
Survey of Automotive Controller Area Network Intrusion Detection Systems. IEEE Des. Test 36 (6) (2019)
Habeeb Olufowobi, Uchenna Ezeobi, Eric Muhati, Gaylon Robinson, Clinton Young, Joseph Zambreno, Gedare Bloom
Anomaly Detection Approach Using Adaptive Cumulative Sum Algorithm for Controller Area Network. AutoSec@CODASPY (2019)
Habeeb Olufowobi, Gedare Bloom, Clinton Young, Joseph Zambreno
Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network. RTSS (2018)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL (2018)
Joe Avey, Phillip H. Jones, Joseph Zambreno
An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig (2018)
Alex Grieve, Michael Davies, Phillip H. Jones, Joseph Zambreno
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. IEEE Trans. Computers 67 (8) (2018)
Xian Zhu, Robert Wernsman, Joseph Zambreno
Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection. ICPP (2018)
Matthew Cauwels, Joseph Zambreno, Phillip H. Jones
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig (2018)
Pei Zhang, Joseph Zambreno, Phillip H. Jones
An embedded scalable linear model predictive hardware-based controller using ADMM. ASAP (2017)
Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. J. Parallel Distributed Comput. 106 (2017)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops (2017)
Xinying Wang, Joseph Zambreno
Parallelizing Latent Semantic Indexing using an FPGA-based architecture. ICCD (2016)
Xian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno
ONAC: Optimal number of active cores detector for energy efficient GPU computing. ICCD (2016)
Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
A Reconfigurable Architecture for the Detection of Strongly Connected Components. ACM Trans. Reconfigurable Technol. Syst. 9 (2) (2016)
Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal
Evidence-based planning to broaden the participation of women in electrical and computer engineering. FIE (2016)
Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. IEEE Trans. Parallel Distributed Syst. 27 (10) (2016)
Aaron Mills, Phillip H. Jones, Joseph Zambreno
Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. IPDPS Workshops (2016)
Xinying Wang, Phillip H. Jones, Joseph Zambreno
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News 43 (4) (2015)
Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. EIT (2015)
Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
A software configurable and parallelized coprocessor architecture for LQR control. ReConFig (2015)
Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Int. J. Reconfigurable Comput. 2015 (2015)
Madhu Monga, Daniel Roggow, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno
Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform. Microprocess. Microsystems 39 (8) (2015)
Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno
A project-based embedded systems design course using a reconfigurable SoC platform. MSE (2015)
Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. ReConFig (2015)
Mihir Awatramani, Xian Zhu, Joseph Zambreno, Diane T. Rover
Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications. PACT (2015)
Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno
An FPGA Architecture for the Recovery of WPA/WPA2 Keys. J. Circuits Syst. Comput. 24 (7) (2015)
Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones
A software configurable coprocessor-based state-space controller. FPL (2015)
Kevin R. Townsend, Joseph Zambreno
A multi-phase approach to floating-point compression. EIT (2015)
Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones
An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. IEEE Embed. Syst. Lett. 6 (1) (2014)
Aaron Mills, Joseph Zambreno
Towards scalable monitoring and maintenance of rechargeable batteries. EIT (2014)
Xinying Wang, Phillip H. Jones, Joseph Zambreno
A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. ISVLSI (2014)
Amit Pande, Shaxun Chen, Prasant Mohapatra, Joseph Zambreno
Hardware Architecture for Video Authentication Using Sensor Pattern Noise. IEEE Trans. Circuits Syst. Video Technol. 24 (1) (2014)
Xinying Wang, Joseph Zambreno
An Efficient Architecture for Floating-Point Eigenvalue Decomposition. FCCM (2014)
N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Cache design for mixed criticality real-time systems. ICCD (2014)
N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Hardware-software architecture for priority queue management in real-time and embedded systems. Int. J. Embed. Syst. 6 (4) (2014)
Mihir Awatramani, Joseph Zambreno, Diane T. Rover
Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications. ICPP Workshops (2014)
Xinying Wang, Joseph Zambreno
An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition. IPDPS Workshops (2014)
Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. IPDPS Workshops (2014)
Kevin Townsend, Phillip H. Jones, Joseph Zambreno
A high performance systolic architecture for k-NN classification. MEMOCODE (2014)
Amit Pande, Joseph Zambreno
A chaotic encryption scheme for real-time embedded systems: design and implementation. Telecommun. Syst. 52 (2) (2013)
Amar Krishna, Joseph Zambreno, Sandeep Krishnan
Polarity Trend Analysis of Public Sentiment on YouTube. COMAD (2013)
Amit Pande, Prasant Mohapatra, Joseph Zambreno
Securing Multimedia Content Using Joint Compression and Encryption. IEEE Multim. 20 (4) (2013)
Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. ICCS (2013)
Mihir Awatramani, Joseph Zambreno, Diane T. Rover
Increasing GPU throughput using kernel interleaved thread block scheduling. ICCD (2013)
Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron, Joseph Zambreno, Phillip H. Jones
Hardware architectural support for control systems and sensor processing. ACM Trans. Embed. Comput. Syst. 13 (2) (2013)
Kevin Townsend, Joseph Zambreno
): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms. ASAP (2013)
Michael Patterson, Aaron Mills, Ryan A. Scheel, Julie Tillman, Evan Dye, Joseph Zambreno
A multi-faceted approach to FPGA-based Trojan circuit detection. VTS (2013)
Madhu Monga, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno
Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform. ICCS (2012)
Amit Pande, Joseph Zambreno
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression. ACM Trans. Embed. Comput. Syst. 11 (1) (2012)
Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno
Shepard: A fast exact match short read aligner. MEMOCODE (2012)
Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Improving System Predictability and Performance via Hardware Accelerated Data Structures. ICCS (2012)
Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno
Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD (2012)
Amit Pande, Joseph Zambreno
The secure wavelet transform. J. Real Time Image Process. 7 (2) (2012)
Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2012)
Alex Baumgarten, Michael Steffen, Matthew Clausman, Joseph Zambreno
A case study in hardware Trojan design and implementation. Int. J. Inf. Sec. 10 (1) (2011)
Amit Pande, Prasant Mohapatra, Joseph Zambreno
Using Chaotic Maps for Encrypting Image and Video Content. ISM (2011)
Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD (2011)
Amit Pande, Joseph Zambreno
Efficient mapping and acceleration of AES on custom multi-core architectures. Concurr. Comput. Pract. Exp. 23 (4) (2011)
Amit Pande, Joseph Zambreno, Prasant Mohapatra
Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. ISVLSI (2011)
Song Sun, Joseph Zambreno
Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining. IEEE Trans. Parallel Distributed Syst. 22 (9) (2011)
Michael Steffen, Phillip H. Jones, Joseph Zambreno
Teaching graphics processing and architecture using a hardware prototyping approach. MSE (2011)
Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno
Preventing IC Piracy Using Reconfigurable Logic Barriers. IEEE Des. Test Comput. 27 (1) (2010)
Michael Steffen, Joseph Zambreno
A hardware pipeline for accelerating ray traversal algorithms on streaming processors. SASP (2010)
Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno
CANSCID-CUDA. MEMOCODE (2010)
Amit Pande, Joseph Zambreno
Reconfigurable hardware implementation of a modified chaotic filter bank scheme. Int. J. Embed. Syst. 4 (3/4) (2010)
Amit Pande, Joseph Zambreno
A Reconfigurable Architecture for Secure Multimedia Delivery. VLSI Design (2010)
Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
Detecting/preventing information leakage on the memory bus due to malicious hardware. DATE (2010)
Michael Steffen, Joseph Zambreno
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. MICRO (2010)
Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
Providing secure execution environments with a last line of defense against Trojan circuit attacks. Comput. Secur. 28 (7) (2009)
Amit Pande, Joseph Zambreno
Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores. CSE (2) (2009)
Song Sun, Zijun Yan, Joseph Zambreno
Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems. Integr. Comput. Aided Eng. 16 (2) (2009)
Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
Hardware-enforced fine-grained isolation of untrusted code. SecuCode@CCS (2009)
Amit Pande, Joseph Zambreno
An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform. ISVLSI (2009)
Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems. CSE (2) (2009)
Jesse Sathre, Alex Baumgarten, Joseph Zambreno
Architectural Support for Automated Software Attack Detection, Recovery, and Prevention. CSE (2) (2009)
Michael Steffen, Joseph Zambreno
Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure. TPCG (2009)
Song Sun, Michael Steffen, Joseph Zambreno
A Reconfigurable Platform for Frequent Pattern Mining. ReConFig (2008)
Song Sun, Zijun Yan, Joseph Zambreno
Experiments in attacking FPGA-based embedded systems using differential power analysis. EIT (2008)
Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
Evaluating the effects of cache redundancy on profit. MICRO (2008)
Jesse Sathre, Joseph Zambreno
Automated software attack recovery using rollback and huddle. Des. Autom. Embed. Syst. 12 (3) (2008)
Amit Pande, Joseph Zambreno
Polymorphic wavelet architectures using reconfigurable hardware. FPL (2008)
Abhishek Das, David Nguyen, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
An FPGA-Based Network Intrusion Detection Architecture. IEEE Trans. Inf. Forensics Secur. 3 (1) (2008)
Amit Pande, Joseph Zambreno
Design and analysis of efficient reconfigurable wavelet filters. EIT (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Joseph Zambreno