An FPGA-based Hardware Accelerator for Iris Segmentation.
Joe AveyPhillip H. JonesJoseph ZambrenoPublished in: ReConFig (2018)
Keyphrases
- field programmable gate array
- iris segmentation
- hardware implementation
- iris recognition
- hardware architecture
- hardware design
- embedded systems
- image processing algorithms
- recognition process
- parallel computing
- low cost
- computing systems
- circular hough transform
- noisy images
- curve evolution
- iris images
- localization algorithm
- signal processing
- feature vectors
- image processing