Phillip H. Jones

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 31

Top Topics

Piecewise Affine

Iris Segmentation

Reconfigurable Architecture

Top Venues

IPDPS Workshops

Publications

Alexis A. Aurandt, Phillip H. Jones, Kristin Yvonne Rozier, Tichakorn Wongpiromsarn
Multimodal Model Predictive Runtime Verification for Safety of Autonomous Cyber-Physical Systems. FMICS (2024)
Gokul Hariharan, Phillip H. Jones, Kristin Yvonne Rozier, Tichakorn Wongpiromsarn
Maximum Satisfiability of Mission-Time Linear Temporal Logic. FORMATS (2023)
Diane T. Rover, Henry Duwe, Phillip H. Jones, Nicholas D. Fila, Mani Mina
Case Studies in Applying Design Thinking to Course Design in Computer Engineering. FIE (2023)
Chris Johannsen, Phillip H. Jones, Brian Kempa, Kristin Yvonne Rozier, Pei Zhang
R2U2 Version 3.0: Re-Imagining a Toolchain for Specification, Resource Estimation, and Optimized Observer Generation for Runtime Verification in Hardware and Software. CAV (3) (2023)
Chris Johannsen, Brian Kempa, Phillip H. Jones, Kristin Y. Rozier, Tichakorn Wongpiromsarn
Impossible Made Possible: Encoding Intractable Specifications via Implied Domain Constraints. FMICS (2023)
Pei Zhang, Alexis A. Aurandt, Rohit Dureja, Phillip H. Jones, Kristin Yvonne Rozier
Model Predictive Runtime Verification for Cyber-Physical Systems with Real-Time Deadlines. FORMATS (2023)
Abigail Hammer, Matthew Cauwels, Benjamin Hertz, Phillip H. Jones, Kristin Y. Rozier
Integrating runtime verification into an automated UAS traffic management system. Innov. Syst. Softw. Eng. 18 (4) (2022)
Alexis A. Aurandt, Phillip H. Jones, Kristin Yvonne Rozier
Runtime Verification Triggers Real-Time, Autonomous Fault Recovery on the CySat-I. NFM (2022)
Henry Duwe, Diane T. Rover, Phillip H. Jones, Nicholas D. Fila, Mani Mina
Defining and Supporting a Debugging Mindset in Computer Engineering Courses. FIE (2022)
Gokul Hariharan, Brian Kempa, Tichakorn Wongpiromsarn, Phillip H. Jones, Kristin Y. Rozier
MLTL Multi-type (MLTLM): A Logic for Reasoning About Signals of Different Types. NSV/FoMLAS@CAV (2022)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP (2021)
Diane T. Rover, Henry J. Duwe III, Mani Mina, Nicholas D. Fila, Phillip H. Jones, Lindsey S. Sleeth
Learning and Professional Development Through Integrated Reflective Activities in Electrical and Computer Engineering Courses. FIE (2021)
Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113 (2021)
Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno
ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. ASAP (2020)
Diane T. Rover, Nicholas D. Fila, Phillip H. Jones, Mani Mina
Introducing Autonomy in an Embedded Systems Course Project. FIE (2020)
Brian Kempa, Pei Zhang, Phillip H. Jones, Joseph Zambreno, Kristin Yvonne Rozier
Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. FORMATS (2020)
Matthew Cauwels, Abigail Hammer, Benjamin Hertz, Phillip H. Jones, Kristin Y. Rozier
Integrating Runtime Verification into an Automated UAS Traffic Management System. ECSA Companion (2020)
Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR (2019)
Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS (2019)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM (2019)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL (2018)
Joe Avey, Phillip H. Jones, Joseph Zambreno
An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig (2018)
Alex Grieve, Michael Davies, Phillip H. Jones, Joseph Zambreno
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. IEEE Trans. Computers 67 (8) (2018)
Matthew Cauwels, Joseph Zambreno, Phillip H. Jones
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig (2018)
Pei Zhang, Joseph Zambreno, Phillip H. Jones
An embedded scalable linear model predictive hardware-based controller using ADMM. ASAP (2017)
Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. J. Parallel Distributed Comput. 106 (2017)
Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops (2017)
Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
A Reconfigurable Architecture for the Detection of Strongly Connected Components. ACM Trans. Reconfigurable Technol. Syst. 9 (2) (2016)
Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal
Evidence-based planning to broaden the participation of women in electrical and computer engineering. FIE (2016)
Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. IEEE Trans. Parallel Distributed Syst. 27 (10) (2016)
Aaron Mills, Phillip H. Jones, Joseph Zambreno
Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. IPDPS Workshops (2016)
Xinying Wang, Phillip H. Jones, Joseph Zambreno
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News 43 (4) (2015)
Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. EIT (2015)
Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
A software configurable and parallelized coprocessor architecture for LQR control. ReConFig (2015)
Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Int. J. Reconfigurable Comput. 2015 (2015)
Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno
A project-based embedded systems design course using a reconfigurable SoC platform. MSE (2015)
Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. ReConFig (2015)
Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno
An FPGA Architecture for the Recovery of WPA/WPA2 Keys. J. Circuits Syst. Comput. 24 (7) (2015)
Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones
A software configurable coprocessor-based state-space controller. FPL (2015)
Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones
A Fault-Aware Toolchain Approach for FPGA Fault Tolerance. ACM Trans. Design Autom. Electr. Syst. 20 (2) (2015)
Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones
An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. IEEE Embed. Syst. Lett. 6 (1) (2014)
Xinying Wang, Phillip H. Jones, Joseph Zambreno
A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. ISVLSI (2014)
N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Cache design for mixed criticality real-time systems. ICCD (2014)
N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Hardware-software architecture for priority queue management in real-time and embedded systems. Int. J. Embed. Syst. 6 (4) (2014)
Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. IPDPS Workshops (2014)
Kevin Townsend, Phillip H. Jones, Joseph Zambreno
A high performance systolic architecture for k-NN classification. MEMOCODE (2014)
Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. ICCS (2013)
Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron, Joseph Zambreno, Phillip H. Jones
Hardware architectural support for control systems and sensor processing. ACM Trans. Embed. Comput. Syst. 13 (2) (2013)
Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno
Shepard: A fast exact match short read aligner. MEMOCODE (2012)
Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
Improving System Predictability and Performance via Hardware Accelerated Data Structures. ICCS (2012)
Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno
Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD (2012)
Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2012)
Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD (2011)
Moinuddin Sayed, Phillip H. Jones
Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers. ReConFig (2011)
Michael Steffen, Phillip H. Jones, Joseph Zambreno
Teaching graphics processing and architecture using a hardware prototyping approach. MSE (2011)
Sudhanshu Vyas, Pooja Mhapsekar, Aditya Ashok, Moinuddin Sayed, Avinash Srinivasa, Gunjan Pandey, Adam Jackson, Matthew Nelson, Anand Saggi, Harini Sundararaman, Phillip H. Jones
Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest. MEMOCODE (2010)
Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno
CANSCID-CUDA. MEMOCODE (2010)
Adwait Gupte, Phillip H. Jones
An evaluation of a slice fault aware tool chain. DATE (2010)
Adwait Gupte, Phillip H. Jones
Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance. ReConFig (2009)
Adwait Gupte, Phillip H. Jones
Towards Hardware Support for Common Sensor Processing Tasks. RTCSA (2009)
Phillip H. Jones, Young H. Cho, John W. Lockwood
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads. VLSI Design (2007)
Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood
Changing Output Quality for Thermal Management. FCCM (2007)
Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood
Adaptive Thermoregulation for Applications on Reconfigurable Devices. FPL (2007)
Phillip H. Jones, John W. Lockwood, Young H. Cho
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications. FPL (2006)
Phillip H. Jones, Young H. Cho, John W. Lockwood
An adaptive frequency control method using thermal feedback for reconfigurable hardware applications. FPT (2006)
Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood
Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. Int. J. Parallel Program. 33 (2-3) (2005)
Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. MSE (2005)
Phillip H. Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, Ron Cytron
Liquid Architecture. IPDPS Next Generation Software Program - NSFNGS - PI Workshop (2004)