Vinod Kathail

Publication Activity (10 Years)

Years Active: 1993-2020
Publications (10 Years): 4

Top Venues

FPGA

IEEE Micro

Hot Chips Symposium

Massachusetts Institute of Technology, Cambridge, MA, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, MA, USA

PHD

Publications

Vinod Kathail
Xilinx Vitis Unified Software Platform. FPGA (2020)
Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro 36 (2) (2016)
Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo
SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. FPGA (2016)
Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
UltraScale+ MPSoC and FPGA families. Hot Chips Symposium (2015)
Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro
Programming high performance signal processing systems in high level languages. FPGA (2010)
Vinod Kathail, Tom Miller
Architecture Exploration for Low Power Design. VLSI Design (2008)
Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar
Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. VLSI Design (2007)
Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
PICO: Automatically Designing Custom Computers. Computer 35 (9) (2002)
Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. J. VLSI Signal Process. 31 (2) (2002)
Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau
Compiling for EPIC architectures. Proc. IEEE 89 (11) (2001)
Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP (2000)
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS (1999)
Hansoo Kim, Vinod Kathail, Kanchi Gopinath, Bhagirath Narahari
Fine Grained Register Allocation for EPIC Processors With Predication. PDPTA (1999)
B. Ramakrishna Rau, Vinod Kathail, Shail Aditya
Machine-Description Driven Compilers for EPIC and VLIW Processors. Des. Autom. Embed. Syst. 4 (2-3) (1999)
Hansoo Kim, Kanchi Gopinath, Vinod Kathail
Register allocation in hyper-block for EPIC processors. PARCO (1999)
Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
Meld Scheduling: A Technique for Relaxing Scheduling Constraints. Int. J. Parallel Program. 26 (4) (1998)
Michael S. Schlansker, Vinod Kathail
Techniques for critical path reduction of scalar programs. Int. J. Parallel Program. 25 (3) (1997)
Michael S. Schlansker, Vinod Kathail, Sadun Anik
Parallelization of Control Recurrences for ILP Processors. Int. J. Parallel Program. 24 (1) (1996)
Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. MICRO (1996)
Michael S. Schlansker, Vinod Kathail
Critical path reduction for scalar programs. MICRO (1995)
Michael S. Schlansker, Vinod Kathail, Sadun Anik
Height reduction of control recurrences for ILP processors. MICRO (1994)
Michael S. Schlansker, Vinod Kathail
Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC (1993)

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Publication Activity (10 Years)

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Vinod Kathail