B. Ramakrishna Rau

Publication Activity (10 Years)

Years Active: 1976-2002
Publications (10 Years): 0

Publications

Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
Constructing and exploiting linear schedules with prescribed parallelism. ACM Trans. Design Autom. Electr. Syst. 7 (1) (2002)
Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
PICO: Automatically Designing Custom Computers. Computer 35 (9) (2002)
Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. J. VLSI Signal Process. 31 (2) (2002)
Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau
Compiling for EPIC architectures. Proc. IEEE 89 (11) (2001)
B. Ramakrishna Rau, Michael S. Schlansker
Embedded Computer Architecture and Automation. Computer 34 (4) (2001)
Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
A Constructive Solution to the Juggling Problem in Processor Array Synthesis. IPDPS (2000)
Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP (2000)
B. Ramakrishna Rau, Michael S. Schlansker
Embedded Computing: New Directions in Architecture and Automation. HiPC (2000)
Michael S. Schlansker, B. Ramakrishna Rau
EPIC: Explicititly Parallel Instruction Computing. Computer 33 (2) (2000)
B. Ramakrishna Rau
The era of embedded computing. CASES (2000)
Santosh G. Abraham, B. Ramakrishna Rau
Efficient design space exploration in PICO. CASES (2000)
Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ACM Trans. Design Autom. Electr. Syst. 5 (4) (2000)
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS (1999)
B. Ramakrishna Rau, Vinod Kathail, Shail Aditya
Machine-Description Driven Compilers for EPIC and VLIW Processors. Des. Autom. Embed. Syst. 4 (2-3) (1999)
John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
Optimization of Machine Descriptions for Efficient Use. Int. J. Parallel Program. 26 (4) (1998)
Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
Region-based compilation: Introduction, motivation, and initial experience. Int. J. Parallel Program. 25 (2) (1997)
Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO (1996)
B. Ramakrishna Rau
Iterative Modulo Scheduling. Int. J. Parallel Program. 24 (1) (1996)
John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
Optimization of Machine Descriptions for Efficient Use. MICRO (1996)
Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
Region-based compilation: an introduction and motivation. MICRO (1995)
B. Ramakrishna Rau
Iterative modulo scheduling: an algorithm for software pipelining loops. MICRO (1994)
B. Ramakrishna Rau
Dynamically scheduled VLIW processors. MICRO (1993)
Joseph A. Fisher, B. Ramakrishna Rau
Guest editors' introduction. J. Supercomput. 7 (1-2) (1993)
Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta
Predictability of load/store instruction latencies. MICRO (1993)
B. Ramakrishna Rau, Joseph A. Fisher
Instruction-level parallel processing: History, overview, and perspective. J. Supercomput. 7 (1-2) (1993)
Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11 (4) (1993)
Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau
Reverse If-Conversion. PLDI (1993)
B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
Code generation schema for modulo scheduled loops. MICRO (1992)
B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
Register Allocation for Software Pipelined Loops. PLDI (1992)
Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS (1992)
B. Ramakrishna Rau
Data Flow and Dependence Analysis for Instruction Level Parallelism. LCPC (1991)
B. Ramakrishna Rau
Pseudo-Randomly Interleaved Memory. ISCA (1991)
B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen
The Cydram 5 Stride-Insensitive Memory System. ICPP (1) (1989)
Peter Y.-T. Hsu, B. Ramakrishna Rau, K. J. M. Moriarty
Appucations Development On the Very Long Instruction Word Cydra-5. Int. J. High Perform. Comput. Appl. 3 (3) (1989)
B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle
The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. Computer 22 (1) (1989)
B. Ramakrishna Rau
Cydra 5 Directed Dataflow Architecture. COMPCON (1988)
B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt
Architectural Support for the Efficient Generation of Code for Horizontal Architectures. ASPLOS (1982)
Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker
Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference (1982)
B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard
Efficient code generation for horizontal architectures: Compiler techniques and architectural support. ISCA (1982)
B. Ramakrishna Rau, Christopher D. Glaeser
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. MICRO (1981)
B. Ramakrishna Rau
Program Behavior and the Performance of Interleaved Memories. IEEE Trans. Computers 28 (3) (1979)
B. Ramakrishna Rau
Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. IEEE Trans. Computers 28 (9) (1979)
B. Ramakrishna Rau
Levels of representation of programs and the architecture of universal host machines. MICRO (1978)
B. Ramakrishna Rau, George E. Rossman
The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. ISCA (1977)
B. Ramakrishna Rau
A new philosophy for interconnection on multilayer boards. DAC (1976)