Sorin Dan Cotofana

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 21

Top Topics

Stochastic Resonance

Error Correction

Top Venues

IEEE Trans. Emerg. Top. Comput.

J. Parallel Distributed Comput.

Publications

Nicoleta Cucu Laurencin, Charles Timmermans, Sorin Dan Cotofana
An Energy-Efficient Graphene-based Spiking Neural Network Architecture for Pattern Recognition. ISCAS (2024)
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Trans. Neural Networks Learn. Syst. 32 (4) (2021)
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. CoRR (2020)
He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana
Ultra-Compact, Entirely Graphene-Based Nonlinear Leaky Integrate-and-Fire Spiking Neuron. ISCAS (2020)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Reliability Aware Design and Lifetime Management of Computing Platforms. IEEE Trans. Emerg. Top. Comput. 8 (3) (2020)
He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana
Graphene Nanoribbon-based Synapses with Versatile Plasticity. NANOARCH (2019)
Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
On Basic Boolean Function Graphene Nanoribbon Conductance Mapping. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2019)
He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana
Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model. ISCAS (2019)
Vasileios G. Ntinas, Antonio Rubio, Georgios Ch. Sirakoulis, Sorin Dan Cotofana
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement. ISCAS (2019)
Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps. ISCAS (2018)
Marius Enachescu, Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. IEEE Trans. Emerg. Top. Comput. 6 (2) (2018)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Haar-based interconnect coding for energy effective medium/long range data transport. SoCC (2017)
Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana
LDPC-Based Adaptive Multi-Error Correction for 3D Memories. ICCD (2017)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Fast and accurate workload-level neural network based IC energy consumption estimation. SMACD (2017)
George Razvan Voicu, Sorin Dan Cotofana
High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders. IEEE Trans. Emerg. Top. Comput. 5 (2) (2017)
Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana
Low cost multi-error correction for 3D polyhedral memories. NANOARCH (2017)
Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota
Brownian Circuits: Designs. Int. J. Unconv. Comput. 12 (5-6) (2016)
Nicoleta Cucu Laurenciu, Tushar Gupta, Valentin Savin, Sorin Dan Cotofana
Error Correction Code protected Data Processing Units. NANOARCH (2016)
Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
A shared polyhedral cache for 3D wide-I/O multi-core computing platforms. ISCAS (2015)
Changlin Chen, Marius Enachescu, Sorin Dan Cotofana
Enabling vertical wormhole switching in 3D NoC-bus hybrid systems. DATE (2015)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Low cost and energy, thermal noise driven, probability modulated random number generator. ISCAS (2015)
Mihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana
Energy effective 3D stacked hybrid NEMFET-CMOS caches. NANOARCH (2014)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Critical transistors nexus based circuit-level aging assessment and prediction. J. Parallel Distributed Comput. 74 (6) (2014)
Changlin Chen, Sorin Dan Cotofana
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs. ISVLSI (2014)
Yao Wang, Sorin Dan Cotofana, Liang Fang
Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices. J. Parallel Distributed Comput. 74 (6) (2014)
Marius Enachescu, Mihai Lefter, Antonios Bazigos, Adrian M. Ionescu, Sorin Dan Cotofana
Ultra low power NEMFET based logic. ISCAS (2013)
Edem Kwedzo Bankas, Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
- 1}. ASAP (2013)
Changlin Chen, Sorin Dan Cotofana
An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs. DSD (2013)
Nicoleta Cucu Laurenciu, Yao Wang, Sorin Dan Cotofana
A direct measurement scheme of amalgamated aging effects with novel on-chip sensor. VLSI-SoC (2013)
Changlin Chen, Sorin Dan Cotofana
A low cost method to tolerate soft errors in the NoC router control plane. SoCC (2013)
Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui, Sorin Dan Cotofana
Is TSV-based 3D integration suitable for inter-die memory repair? DATE (2013)
George Razvan Voicu, Sorin Dan Cotofana
Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing. NANOARCH (2013)
Yao Wang, Sorin Dan Cotofana, Liang Fang
Lifetime reliability assessment with aging information from low-level sensors. ACM Great Lakes Symposium on VLSI (2013)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
A nonlinear degradation path dependent end-of-life estimation framework from noisy observations. Microelectron. Reliab. 53 (9-11) (2013)
George Razvan Voicu, Mihai Lefter, Marius Enachescu, Sorin Dan Cotofana
3D stacked wide-operand adders: A case study. ASAP (2013)
Yao Wang, Sorin Dan Cotofana, Liang Fang
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. NANOARCH (2012)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Context aware slope based transistor-level aging model. Microelectron. Reliab. 52 (9-10) (2012)
Saleh Safiruddin, Mihai Lefter, Demid Borodin, George Razvan Voicu, Sorin Dan Cotofana
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits. NANOARCH (2012)
Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
A Markovian, variation-aware circuit-level aging model. NANOARCH (2012)
Changlin Chen, Ye Lu, Sorin Dan Cotofana
A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip. NOCS (2012)
Yao Wang, Marius Enachescu, Sorin Dan Cotofana, Liang Fang
Variation tolerant on-chip degradation sensors for dynamic reliability management systems. Microelectron. Reliab. 52 (9-10) (2012)
Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana
Is the road towards "Zero-Energy" paved with NEMFET-based power management? ISCAS (2012)
George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana
A 3D stacked high performance scalable architecture for 3D Fourier Transform. ICCD (2012)
Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana
An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana
Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs. NANOARCH (2011)
Dennis Andrade, Antonio Rubio, Antonio Calomarde, Sorin Dan Cotofana
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations. ISCAS (2011)
Demid Borodin, Winston Siauw, Sorin Dan Cotofana
Functional unit sharing between stacked processors in 3D integrated systems. ICSAMOS (2011)
Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana
+1} based on a novel RNS representation. ICCD (2010)
Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana
- 1} moduli set. ASAP (2010)
Kazeem Alagbe Gbolagade, Ricardo Chaves, Leonel Sousa, Sorin Dan Cotofana
-1} moduli set. ISCAS (2010)
Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}. ICECS (2009)
Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
Generalized matrix method for efficient residue to decimal conversion. APCCAS (2008)
Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
A residue to binary converter for the {2n + 2, 2n + 1, 2n} moduli set. ACSCC (2008)
Saleh Safiruddin, Sorin Dan Cotofana, Ferdinand Peper
Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits. NANOARCH (2008)
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana
Compositional, dynamic cache management for embedded chip multiprocessors. DATE (2008)
Radu Andrei Stefan, Sorin Dan Cotofana
Bitstream compression techniques for Virtex 4 FPGAs. FPL (2008)
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
Compositional Memory Systems for Multimedia Communicating Tasks CoRR (2007)
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors. Trans. High Perform. Embed. Archit. Compil. 1 (2007)
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
Compositional, efficient caches for a chip multi-processor. DATE (2006)
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
Throughput optimization via cache partitioning for embedded multiprocessors. ICSAMOS (2006)
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
Static cache partitioning robustness analysis for embedded on-chip multi-processors. Conf. Computing Frontiers (2006)
Sorin Dan Cotofana, Casper Lageweg, Stamatis Vassiliadis
Addition Related Arithmetic Operations via Controlled Transport of Charge. IEEE Trans. Computers 54 (3) (2005)
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
Compositional Memory Systems for Multimedia Communicating Tasks. DATE (2005)
Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang
Analysis of analog to digital converter based on single-electron tunnelling transistors. ISCAS (3) (2004)
Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
Pel reconstruction on FPGA-augmented TriMedia. IEEE Trans. Very Large Scale Integr. Syst. 12 (6) (2004)
Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang
Single-electron tunneling transistor implementation of periodic symmetric functions. IEEE Trans. Circuits Syst. II Express Briefs (11) (2004)
Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang, Qiyu Cai
Analog-to-digital converter based on single-electron tunneling transistors. IEEE Trans. Very Large Scale Integr. Syst. 12 (11) (2004)
Peter Celinski, Derek Abbott, Sorin Dan Cotofana
Area efficient, high speed parallel counter circuits using charge recycling threshold logic. ISCAS (5) (2003)