Mihai Lefter

Publication Activity (10 Years)

Years Active: 2012-2021
Publications (10 Years): 4

Top Topics

Computing Platform

Error Correction

Top Venues

Publications

Mihai Lefter, Jonathan K. Vis, Martijn Vermaat, Johan T. den Dunnen, Peter E. M. Taschner, Jeroen F. J. Laros
Mutalyzer 2: next generation HGVS nomenclature checker. Bioinform. 37 (18) (2021)
Marius Enachescu, Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. IEEE Trans. Emerg. Top. Comput. 6 (2) (2018)
Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana
LDPC-Based Adaptive Multi-Error Correction for 3D Memories. ICCD (2017)
Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana
Low cost multi-error correction for 3D polyhedral memories. NANOARCH (2017)
Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
A shared polyhedral cache for 3D wide-I/O multi-core computing platforms. ISCAS (2015)
Mihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana
Energy effective 3D stacked hybrid NEMFET-CMOS caches. NANOARCH (2014)
Marius Enachescu, Mihai Lefter, Antonios Bazigos, Adrian M. Ionescu, Sorin Dan Cotofana
Ultra low power NEMFET based logic. ISCAS (2013)
Mottaqiallah Taouil, Mihai Lefter, Said Hamdioui
Exploring test opportunities for memory and interconnects in 3D ICs. IDT (2013)
Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui, Sorin Dan Cotofana
Is TSV-based 3D integration suitable for inter-die memory repair? DATE (2013)
George Razvan Voicu, Mihai Lefter, Marius Enachescu, Sorin Dan Cotofana
3D stacked wide-operand adders: A case study. ASAP (2013)
Saleh Safiruddin, Mihai Lefter, Demid Borodin, George Razvan Voicu, Sorin Dan Cotofana
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits. NANOARCH (2012)