Yasuo Takahashi

Publication Activity (10 Years)

Years Active: 2000-2017
Publications (10 Years): 2

Top Topics

Printed Circuit

Analog Circuits

Associative Search

Top Venues

Int. J. Unconv. Comput.

IEICE Trans. Electron.

Publications

Mika Laiho, Mika Grönroos, Jussi H. Poikonen, Eero Lehtonen, Reon Katsumura, Atsushi T.-Fukuchi, Masashi Arita, Yasuo Takahashi
Associative search using pseudo-analog memristors. ISCAS (2017)
Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota
Brownian Circuits: Designs. Int. J. Unconv. Comput. 12 (5-6) (2016)
Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi
Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device. IEICE Trans. Electron. (5) (2012)
Masakatsu Maeda, Takaaki Sato, Naoto Inoue, Daisuke Yagi, Yasuo Takahashi
Anomalous microstructure formed at the interface between copper ribbon and tin-deposited copper plate by ultrasonic bonding. Microelectron. Reliab. 51 (1) (2011)
Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. Int. J. Nanotechnol. Mol. Comput. 1 (2) (2009)
Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu
Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors. IEICE Trans. Electron. (5) (2007)
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. 13 (3) (2007)
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL (2006)
Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL (2005)
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL (2004)
Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL (2004)
Hiroshi Inokawa, Yasuo Takahashi
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. ISMVL (2003)
Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase
Silicon Single-Electron Devices and Their Applications. ISMVL (2000)