Hiroshi Inokawa

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 9

Top Topics

Nonsubsampled Contourlet Transform

Refractive Index

Silicon On Insulator

Top Venues

IEICE Electron. Express

Publications

Somrita Ghosh, Aritra Acharyya, Arindam Biswas, Amit Banerjee, Hiroshi Inokawa, Hiroaki Satoh, Alexey Y. Seteikin, I. G. Samusev
Multiple Quantum Barrier Avalanche Photodiode Based on GaN/AlGaN Heterostructures for Long Wavelength Infrared Detection. IEEE Access 12 (2024)
Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa
Folded-Dipole Antenna Geometrical Analysis for THz Microbolometer. IEEE Access 11 (2023)
Hiroaki Satoh, Koki Isogai, Shohei Iwata, Taiki Aso, Ryosuke Hayashi, Shu Takeuchi, Hiroshi Inokawa
Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical Biosensor. Sensors 23 (2) (2023)
Hiroaki Satoh, Ken Kawakubo, Atsushi Ono, Hiroshi Inokawa
Angle-sensitive pixel based on silicon-on-insulator p-n junction photodiode with aluminum grating gate electrode. IEICE Electron. Express 19 (21) (2022)
Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa
Responsivity and NEP Improvement of Terahertz Microbolometer by High-Impedance Antenna. Sensors 22 (14) (2022)
Anitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa
Angle-Sensitive Detector Based on Silicon-On-Insulator Photodiode Stacked with Surface Plasmon Antenna. Sensors 20 (19) (2020)
Anitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa
Angular selectivity of SOI photodiode with surface plasmon antenna. IEICE Electron. Express 17 (13) (2020)
Yash Sharma, Hiroaki Satoh, Hiroshi Inokawa
Application of bow-tie surface plasmon antenna to silicon on insulator nanowire photodiode for enhanced light absorption. IEICE Electron. Express 15 (11) (2018)
Hiroshi Inokawa, Norihiro Katayama, Mitsuyuki Nakao
Evaluation of multidrug cancer chronotherapy based on cell cycle model under influences of circadian clock. EMBC (2016)
Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi
Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device. IEICE Trans. Electron. (5) (2012)
Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. Int. J. Nanotechnol. Mol. Comput. 1 (2) (2009)
Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu
Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors. IEICE Trans. Electron. (5) (2007)
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. 13 (3) (2007)
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL (2006)
Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL (2005)
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL (2004)
Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL (2004)
Hiroshi Inokawa, Yasuo Takahashi
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. ISMVL (2003)
Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya
A 0.5-V MTCMOS/SIMOX logic gate. IEEE J. Solid State Circuits 32 (10) (1997)