Satoshi Shigematsu

Publication Activity (10 Years)

Years Active: 1995-2020
Publications (10 Years): 8

Top Topics

Mobile Communications

Resource Scheduling

Cmos Image Sensor

Top Venues

Publications

Kota Shikama, Norio Sato, Atsushi Aratake, Satoshi Shigematsu, Takeshi Sakamoto
Miniature Optical Connector with Magnetic Physical Contact. OFC (2020)
Yuki Arikawa, Takeshi Sakamoto, Satoshi Shigematsu
Hierarchical Scheduling with FPGA-based Accelerator for Flexible 5G Mobile Networks. VTC Spring (2020)
Kazunari Kurita, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda, Yoshihiro Koga
Proximity Gettering Design of Hydrocarbon-Molecular-Ion-Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors. Sensors 19 (9) (2019)
Morihiko Minowa, Hiroyuki Seki, Yukihiko Okumura, Satoshi Suyama, Jun Terada, Satoshi Shigematsu, Yasushi Takatori, Hiroaki Asano, Yukio Hirano, Yasushi Yamao, Fumiyuki Adachi, Masataka Nakazawa
5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells. VTC Spring (2019)
Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu
Throughput Enhancement with Hardware Accelerated Resource Scheduler in Low-Latency 5G Systems. PIMRC (2018)
Salah Ibrahim, Toshikazu Hashimoto, Satoshi Shigematsu
Contention-Less Scheduling-Free Torus Optical Network Comprising Thousands of Nodes. ECOC (2018)
Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda
A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2017)
Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu
High-speed radio-resource scheduling for 5G ultra-high-density distributed antenna systems. WCSP (2016)
Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. IEICE Trans. Electron. (1) (2015)
Yuki Arikawa, Kenji Kawai, Hiroyuki Uzawa, Satoshi Shigematsu
Practical resource scheduling in massive-cell deployment for 5G mobile communications systems. ISPACS (2015)
Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Satoshi Shigematsu
High-speed sorted-table search scheme for network processing. APCC (2015)
Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda
A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. ISPACS (2015)
Hiroyuki Uzawa, Yuki Arikawa, Kenji Kawai, Satoshi Shigematsu
Data transmission scheme for enhancing effective downlink bandwidth in 5G mobile fronthaul with TDM-PON. ECOC (2015)
Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu
Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC. ReConFig (2014)
Takayoshi Tashiro, Shigeru Kuwano, Jun Terada, Tomoaki Kawamura, Nobuyuki Tanaka, Satoshi Shigematsu, Naoto Yoshimoto
A novel DBA scheme for TDM-PON based mobile fronthaul. OFC (2014)
Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. FPL (2012)
Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 47 (1) (2012)
Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. IEEE J. Solid State Circuits 45 (5) (2010)
Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner
Fusion of MEMS and circuits. ISSCC (2010)
Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi
A Fingerprint Sensor with Impedance Sensing for Fraud Detection. ISSCC (2008)
Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. (10) (2007)
Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. (4) (2006)
Satoshi Shigematsu, Hiroki Morimura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi
Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. (5) (2005)
Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs. IEEE J. Solid State Circuits 37 (10) (2002)
Namiko Ikeda, Mamoru Nakanishi, Koji Fujii, Takahiro Hatano, Satoshi Shigematsu, Takuya Adachi, Yukio Okazaki, Hakaru Kyuragi
Fingerprint Image Enhancement by Pixel-Parallel Processing. ICPR (3) (2002)
Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. CICC (2002)
Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi
A Fingerprint Verification Algorithm Using the Differential Matching Rate. ICPR (3) (2002)
Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida
A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors. IEEE J. Solid State Circuits 35 (5) (2000)
Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka
A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. ISLPED (1999)
Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. ASP-DAC (1999)
Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida
A single-chip fingerprint sensor and identifier. IEEE J. Solid State Circuits 34 (12) (1999)
Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. Solid State Circuits 32 (6) (1997)
Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya
A 0.5-V MTCMOS/SIMOX logic gate. IEEE J. Solid State Circuits 32 (10) (1997)
Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. IEEE J. Solid State Circuits 31 (11) (1996)
Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid State Circuits 30 (8) (1995)