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A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.
Hiroki Morimura
Satoshi Shigematsu
Shinsuke Konaka
Published in:
ISLPED (1999)
Keyphrases
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random access memory
low power
design considerations
ultra low power
software architecture
power consumption
management system
bit parallel
n gram
word pairs
nm technology
real time
high speed
network architecture
cmos technology