Yoshio Matsuda

Publication Activity (10 Years)

Years Active: 1989-2022
Publications (10 Years): 18

Top Topics

Intensity Difference

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Narumi Sugiura, Rikako Ogura, Yoshio Matsuda, Takashi Komuro, Kayo Ogawa
Users' Content Memorization in Multi-User Interactive Public Displays. Int. J. Hum. Comput. Interact. 38 (5) (2022)
Yoshio Matsuda, Takashi Komuro, Takuya Yoda, Hajime Nagahara, Shoji Kawahito, Keiichiro Kagawa
Palm-Controlled Pointing Interface Using a Dynamic Photometric Stereo Camera. HCI (48) (2020)
Yoshio Matsuda, Takashi Komuro
Dynamic layout optimization for multi-user interaction with a large display. IUI (2020)
Kousuke Imamura, Satoshi Kanda, Saya Ohira, Yoshio Matsuda, Tetsuya Matsumura
Scalable Architecture for High-Resolution Real-time Optical Flow Processor. IoTaIS (2019)
Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. ISPACS (2019)
Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. IEICE Trans. Electron. (4) (2019)
Yuriko Sakakibara, Yoshio Matsuda, Takashi Komuro, Kayo Ogawa
Simultaneous interaction with a large display by many users. PerDis (2019)
Yoshio Matsuda, Takashi Komuro
A Multi-user Interactive Public Display with Dynamic Layout Optimization. PerDis (2018)
Reo Aoki, Kousuke Imamura, Akihiro Hirano, Yoshio Matsuda
High-Performance Super-Resolution via Patch-Based Deep Neural Network for Real-Time Implementation. IEICE Trans. Inf. Syst. (11) (2018)
Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. IOTAIS (2018)
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Yu Suzuki, Masato Ito, Satoshi Kanda, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura
Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda
A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2017)
Tetsuya Matsumura, Kousuke Imamura, Yoshifumi Kawamura, Yoshio Matsuda
Automatic rule registration and deletion function on a packet lookup engine LSI. ISPACS (2016)
Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
A study on fast motion estimation algorithm. GCCE (2016)
Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda
A study on motion estimation algorithm for moving pictures. GCCE (2016)
Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2016)
Kousuke Imamura, Naoki Kimura, Fumiaki Satou, Shigeru Sanada, Yoshio Matsuda
Image denoising using non-local means for Poisson noise. ISPACS (2016)
Kousuke Imamura, Kaoru Itoh, Yoshio Matsuda
A fast atom selection method based on the order of initial inner product values for image denoising using sparse representation. ISPACS (2015)
Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda
A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. ISPACS (2015)
Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda
A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm. DDECS (2015)
Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS (2014)
Shunji Nakata, Hiroshi Makino, Yoshio Matsuda
A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. MWSCAS (2014)
Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. J. Circuits Syst. Comput. 23 (3) (2014)
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED (2013)
Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6 (4) (2012)
Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. MWSCAS (2012)
Masayuki Miyama, Yoshio Matsuda
Vehicle detection and tracking with affine motion segmentation in stereo video. ICSIPA (2011)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda
A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications. IEICE Trans. Electron. (5) (2010)
Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express 7 (9) (2010)
Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS (2010)
Shunji Nakata, Masayuki Miyama, Yoshio Matsuda
Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system. IET Circuits Devices Syst. 4 (4) (2010)
Yoshiki Yunbe, Masayuki Miyama, Yoshio Matsuda
A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation. IEICE Trans. Inf. Syst. (12) (2010)
Shunji Nakata, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda
Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage. ISCAS (2009)
Masayuki Miyama, Yuusuke Inoie, Takafumi Kasuga, Ryouichi Inada, Masashi Nakao, Yoshio Matsuda
A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2008)
Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. (4) (2008)
Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35 (5) (2000)
Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda
Novel VLIW code compaction method for a 3D geometry processor. CICC (2000)
Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
The D30V/MPEG multimedia processor. IEEE Micro 19 (4) (1999)
Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34 (4) (1999)
Hideaki Yamanaka, Hirotaka Saito, Harofusa Kondoh, Yasuhito Sasaki, Hirotoshi Yamada, Munenori Tsuzuki, Satoshi Nishio, Hiromi Notani, Atsushi Iwabu, Masahiko Ishiwaki, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima
Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue. IEEE J. Sel. Areas Commun. 15 (5) (1997)
Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. IEEE J. Solid State Circuits 31 (7) (1996)
Hirotaka Saito, Hideaki Yamanaka, Hirotoshi Yamada, Munenori Tsuzuki, Harofusa Kondoh, Yoshio Matsuda, Kazuyoshi Oshima
Multicast Function and its LSI Implementation in a Shared Multibuffer ATM Switch. INFOCOM (1994)
Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima
The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro 10 (2) (1990)
Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
A New Array Architecture for Parallel Testing in VLSI Memories. ITC (1989)