Mikio Asakura

Publication Activity (10 Years)

Years Active: 1990-1996
Publications (10 Years): 0

Publications

Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. IEEE J. Solid State Circuits 31 (4) (1996)
Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits 31 (4) (1996)
Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits 29 (4) (1994)
Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29 (11) (1994)
Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima
The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro 10 (2) (1990)