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The cache DRAM architecture: a DRAM with an on-chip cache memory.
Hideto Hidaka
Yoshio Matsuda
Mikio Asakura
Kazuyasu Fujishima
Published in:
IEEE Micro (1990)
Keyphrases
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memory subsystem
dynamic random access memory
instruction set
ibm zenterprise
main memory
embedded dram
memory access
video decoder
input output
memory hierarchy
secondary storage
cache conscious
ibm power processor
data center
flash memory