Hideto Hidaka

Publication Activity (10 Years)

Years Active: 1986-2020
Publications (10 Years): 6

Top Topics

Utmost Importance

Write Operations

Top Venues

IEICE Trans. Electron.

IEEE J. Solid State Circuits

Publications

Takashi Kono, Yasuhiko Taito, Hideto Hidaka
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age. IEICE Trans. Electron. (4) (2020)
Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. IEICE Trans. Electron. (4) (2019)
Hideto Hidaka
Foreword. IEICE Trans. Electron. (4) (2019)
Hideto Hidaka
Foreword. IEICE Trans. Electron. (4) (2018)
Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. IEEE J. Solid State Circuits 51 (1) (2016)
Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. ISSCC (2016)
Hideto Hidaka
How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology. A-SSCC (2015)
Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. ISSCC (2015)
Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. IEEE J. Solid State Circuits 49 (1) (2014)
Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. ISSCC (2013)
Anantha P. Chandrakasan, Hideto Hidaka
Session 1 overview: Plenary session. ISSCC (2012)
Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai
Silicon 3D-integration technology and systems. ISSCC (2010)
Donhee Ham, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 44 (1) (2009)
Hideto Hidaka, Yair Sofer
Non-Volatile Memories. ISSCC (2007)
Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. ITC (2002)
Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits 37 (7) (2002)
Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. IEEE J. Solid State Circuits 36 (11) (2001)
Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka
A shared built-in self-repair analysis for multiple embedded memories. CICC (2001)
Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka
A built-in self-repair analyzer (CRESTA) for embedded DRAMs. ITC (2000)
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34 (8) (1999)
Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits 31 (4) (1996)
Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. IEEE J. Solid State Circuits 30 (4) (1995)
Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits 29 (4) (1994)
Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits 29 (11) (1994)
Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29 (11) (1994)
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10 (2) (1993)
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC (1992)
Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima
The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro 10 (2) (1990)
Y. Nishimura, Mitsuhiro Hamada, Hideto Hidaka, H. Ozaki, Kazuyasu Fujishima, Y. Hayasaka
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. ITC (1986)