Toshiaki Kawasaki

Publication Activity (10 Years)

Years Active: 2001-2007
Publications (10 Years): 0

Publications

Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Trans. Electron. (5) (2007)
Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi
A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process. IEEE J. Solid State Circuits 40 (5) (2005)
Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits 37 (7) (2002)
Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. IEEE J. Solid State Circuits 36 (11) (2001)