A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process.
Masanori ShirahamaYasuhiro AgataToshiaki KawasakiRyuji NishiharaWataru AbeNaoki KurodaHiroyuki SadakataToshitaka UchikobaKazunari TakahashiKyoko EgashiraShinji HondaMiho MiuraShin HashimotoHirohito KikukawaHiroyuki YamauchiPublished in: IEEE J. Solid State Circuits (2005)