0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.
Hirohito KikukawaShigeki TomishimaTakaharu TsujiToshiaki KawasakiShouji SakamotoMasatoshi IshikawaWataru AbeHiroaki TanizakiHiroshi KatoToshitaka UchikobaToshihiro InokuchiManabu SenohYoshifumi FukushimaMitsutaka NiiroMasanao MarutaAkinori ShibayamaTsukasa OoishiKazunari TakahashiHideto HidakaPublished in: IEEE J. Solid State Circuits (2002)