Masanao Maruta

Publication Activity (10 Years)

Years Active: 2001-2005
Publications (10 Years): 0

Publications

Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits 40 (11) (2005)
Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. ITC (2002)
Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits 37 (7) (2002)
Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. IEEE J. Solid State Circuits 36 (11) (2001)
Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka
A shared built-in self-repair analysis for multiple embedded memories. CICC (2001)