A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.
Yasue YamamotoMasanori ShirahamaToshiaki KawasakiRyuji NishiharaShinichi SumiYasuhiro AgataHirohito KikukawaHiroyuki YamauchiPublished in: IEICE Trans. Electron. (2007)
Keyphrases
- flip flops
- power dissipation
- cmos technology
- nm technology
- power consumption
- design process
- low power
- multiple input
- architectural design
- chip design
- design methodology
- information retrieval
- circuit design
- software architecture
- high speed
- main memory
- embedded dram
- digital signal processing
- low cost
- cmos image sensor
- analog to digital converter
- low voltage
- memory hierarchy
- hardware architecture
- design considerations
- design principles
- parallel processing
- logic programming
- management system